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lsi53CF92A fast scsi controller technical manual april 2002 version 2.1
ii copyright 1995?002 by lsi logic corporation. all rights reserved. this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?er of lsi logic corporation. lsi logic products are not intended for use in life-support appliances, devices, or systems. use of any lsi logic product in such applications without written consent of the appropriate lsi logic of?er is prohibited. document db14-000094-02, third edition (april 2002) this document describes the lsi logic lsi53CF92A fast scsi controller and will remain the of?ial reference source for all revisions of this product until rescinded by an update. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright 1995?002 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design, scripts, sym, and tolerant are trademarks or registered trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. ap to receive product literature, visit us at http://www.lsilogic.com. for a current list of our distributors, sales of?es, and design resource centers, view our web page located at http://www.lsilogic.com/contacts/na_salesof?es.html
lsi53CF92A fast scsi controller iii copyright 1995?002 by lsi logic corporation. all rights reserved. preface this book is the primary reference and technical manual for the lsi53CF92A fast scsi controller. it contains a complete functional description and includes complete physical and electrical speci?ations. audience this document assumes that you have some familiarity with current and proposed scsi standards. the people who bene? from this book are: ? engineers and managers who are evaluating the controller for possible use in a system ? engineers who are designing the controller into a system organization this document has the following chapters and appendixes: ? chapter 1, introduction ? chapter 2, functional description ? chapter 3, signal descriptions ? chapter 4, registers ? chapter 5, command set ? chapter 6, electrical speci?ations ? appendix a, register map ? appendix b, wiring diagram
iv preface copyright 1995?002 by lsi logic corporation. all rights reserved. related publications ansi 11 west 42nd street new york, ny 10036 (212) 642-4900 document no. x3.131-199x (scsi-2) global engineering documents 15 inverness way east englewood, co 80112 (800) 854-7179 or (303) 397-7956 (outside u.s.) fax (303) 397-2740 endl publications 14426 black walnut court saratoga, ca 95070 (408) 867-6642 document names: scsi bench reference, scsi encyclopedia, scsi tutor prentice hall 113 sylvan avenue englewood cliffs, nj 07632 (800) 947-7700 scsi: understanding the small computer system interface, isbn 0-13-796855-8 lsi logic world wide web home page www.lsil.com scsi scripts processors programming guide , order no. s14044.a scam speci?ation x3t9.2/93-109r5 pci special interest group 2575 n. e. katherine hillsboro, or 97214 (800) 433-5177; (503) 693-6232 (international); fax (503) 693-8344
preface v copyright 1995?002 by lsi logic corporation. all rights reserved. conventions used in this manual the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. hexadecimal numbers are indicated by the pre? ?x ?or example, 0x32cf. binary numbers are indicated by the pre? ?b ?or example, 0b0011.0010.1100.1111. revision record revision date remarks 1.0 12/97 first version. 1.1 4/99 miscellaneous edits, reformat. 2.0 11/00 all product names changed from sym to lsi. 2.1 12/01 updated tables 6.7, 6.13, and 6.15 and figures 6.9, 6.12, and 6.16.
vi preface copyright 1995?002 by lsi logic corporation. all rights reserved.
lsi53CF92A fast scsi controller vii copyright 1995?002 by lsi logic corporation. all rights reserved. contents chapter 1 introduction 1.1 general description 1-1 1.2 scsi-con?ured automatically (scam) capability 1-2 1.3 tolerant technology 1-2 1.4 features 1-3 chapter 2 functional description 2.1 typical scsi operation 2-2 2.2 bus-initiated sequences 2-3 2.2.1 bus-initiated selection 2-4 2.2.2 bus-initiated reselection 2-5 2.2.3 bus-initiated reset 2-6 2.2.4 stacked commands 2-6 2.3 parity checking and generation 2-6 2.4 host bus con?uration 2-8 2.4.1 mode description 2-8 2.4.2 multiplexed bus con?uration mode 2-8 2.4.3 nonmultiplexed bus con?uration mode 2-9 2.5 dma operation 2-9 2.5.1 dma threshold 2-9 2.5.2 normal dma mode 2-9 2.5.3 threshold eight mode 2-10 2.5.4 dma burst mode 2-11 2.5.5 single-pin, se scsi 2-13 2.6 scsi data transfer rates 2-14 2.6.1 asynchronous operation 2-14 2.6.2 synchronous operation 2-14 2.7 chip reset 2-15
viii contents copyright 1995?002 by lsi logic corporation. all rights reserved. 2.7.1 hard reset 2-15 2.7.2 soft reset 2-16 2.7.3 disconnect reset 2-17 2.8 scam capabilities 2-17 2.8.1 scsi low-level programming 2-18 2.8.2 scam operations 2-18 chapter 3 signal descriptions chapter 4 registers 4.1 standard register set 4-4 4.2 scam register set 4-36 chapter 5 command set 5.1 illegal commands 5-3 5.1.1 stacked commands 5-3 5.2 miscellaneous command group 5-4 5.2.1 no-operation (nop) 5-4 5.2.2 flush fifo 5-4 5.2.3 reset chip 5-4 5.2.4 reset scsi bus 5-5 5.2.5 disable selection/reselection 5-5 5.3 disconnected state command group 5-5 5.3.1 reselect sequence 5-6 5.3.2 select without atn sequence 5-6 5.3.3 select with atn sequence 5-7 5.3.4 select with atn and stop sequence 5-7 5.3.5 enable selection/reselection 5-11 5.3.6 select with atn3 sequence 5-11 5.3.7 reselect3 sequence 5-12 5.4 initiator command group 5-12 5.4.1 transfer information 5-14 5.4.2 initiator command complete sequence 5-15 5.4.3 message accepted 5-15 5.4.4 transfer pad 5-16 5.4.5 set atn 5-16 5.4.6 reset atn 5-16 5.4.7 set atn immediate 5-17
contents ix copyright 1995?002 by lsi logic corporation. all rights reserved. 5.5 target command group 5-17 5.5.1 send message 5-18 5.5.2 send status 5-18 5.5.3 send data 5-18 5.5.4 disconnect sequence 5-19 5.5.5 terminate sequence 5-19 5.5.6 target command complete sequence 5-20 5.5.7 disconnect 5-20 5.5.8 receive message 5-21 5.5.9 receive command 5-21 5.5.10 receive data 5-21 5.5.11 receive command sequence 5-21 5.5.12 target abort dma 5-22 chapter 6 electrical speci?ations 6.1 dc electrical characteristics 6-1 6.2 tolerant active negation technology speci?ations 6-4 6.3 ac electrical characteristics 6-7 6.3.1 register interface, nonmultiplexed pad bus 6-11 6.3.2 register interface, multiplexed pad bus 6-13 6.3.3 dma interface (nonmultiplexed mode only) 6-15 6.3.4 dma interface (multiplexed mode only) 6-17 6.3.5 burst mode dma interface (multiplexed mode) 6-19 6.3.6 burst mode dma interface (nonmultiplexed mode) 6-21 6.4 scsi timing diagrams 6-23 6.5 package drawings 6-29 appendix a register map appendix b wiring diagram index customer feedback
x contents copyright 1995?002 by lsi logic corporation. all rights reserved.
contents xi copyright 1995?002 by lsi logic corporation. all rights reserved. figures 1.1 functional block diagram 1-4 1.2 bus con?uration, multiplexed mode (dual bus, 8-bit dma bus and 8-bit multiplexed processor address/data bus) 1-5 1.3 bus con?uration, nonmultiplexed mode (dual bus, 8-bit dma bus and 8-bit processor bus) 1-5 2.1 normal dma mode 2-10 2.2 dma burst mode (multiplexed mode and nonmultiplexed mode writes) 2-13 2.3 dma burst mode (nonmultiplexed mode reads) 2-13 2.4 scam transfer cycles 2-23 3.1 functional signal grouping 3-1 3.2 lsi53CF92A 64-pin plastic qfp and thin qfp pin con?uration 1 3-6 4.1 req/ ack/ deassertion delay 4-23 6.1 rise and fall time test conditions 6-5 6.2 scsi input filtering 6-5 6.3 hysteresis of scsi receivers 6-5 6.4 input current as a function of input voltage 6-6 6.5 output current as a function of output voltage 6-6 6.6 clock input 6-8 6.7 reset input 6-9 6.8 interrupt output 6-10 6.9 register read, nonmultiplexed pad bus 6-11 6.10 register write, nonmultiplexed pad bus 6-11 6.11 register read, multiplexed pad bus 6-13 6.12 register write, multiplexed pad bus 6-13 6.13 dma read, nonmultiplexed mode only 6-15 6.14 dma write, nonmultiplexed mode only 6-15 6.15 dma read, multiplexed mode only 6-17 6.16 dma write, multiplexed mode only 6-17 6.17 burst mode dma read, multiplexed mode only 6-19 6.18 burst mode dma write, multiplexed mode only 6-19 6.19 burst mode dma read, nonmultiplexed mode only 6-21 6.20 burst mode dma write, nonmultiplexed mode only 6-21 6.21 initiator asynchronous send 6-23
xii contents copyright 1995?002 by lsi logic corporation. all rights reserved. 6.22 initiator asynchronous receive 6-24 6.23 target asynchronous send 6-25 6.24 target asynchronous receive 6-26 6.25 target and initiator synchronous output 6-27 6.26 target and initiator synchronous input 6-27 6.27 64-pin plastic quad flat pack 6-29 6.28 64-pin thin quad flat pack 6-30 b.1 single-pin, se scsi bus interface wiring diagram b-1
contents xiii copyright 1995?002 by lsi logic corporation. all rights reserved. tables 2.1 parity control 2-7 2.2 minimum timing requirements 2-15 3.1 microprocessor and dma interface signals 3-2 3.2 scsi signals 3-4 3.3 con?uration and test signals 3-5 3.4 power and ground signals 3-5 4.1 register reset values 4-2 4.2 register set 4-3 4.3 transfer rate with 40 mhz clock (fastclk bit set) 4-19 4.4 transfer rate with 25 mhz clock (fastclk bit clear) 4-20 4.5 req/ ack/ deassertion delay selection 4-22 4.6 req/ ack/ assertion delay selection 4-22 4.7 clk frequency vs. clock conversion factor 4-26 4.8 synchronous transfer rate and minimum clocks/byte 4-32 4.9 dma modes 4-32 5.1 command set 5-2 5.2 miscellaneous commands 5-4 5.3 disconnected state commands 5-6 5.4 target selected without atn sequence 5-8 5.5 target selected with atn sequence (scsi-2 bit not set) 5-8 5.6 target selected with atn sequence (scsi-2 bit or queue tag enable bit set) 5-9 5.7 initiator select without atn sequence 5-10 5.8 initiator select with atn sequence 5-10 5.9 initiator select with atn and stop sequence 5-11 5.10 initiator select with atn3 sequence 5-12 5.11 initiator commands 5-14 5.12 target commands 5-18 5.13 target disconnect sequence 5-19 5.14 target terminate sequence 5-20 5.15 target command complete sequence 5-20 5.16 target receive command sequence 5-22 6.1 absolute maximum stress ratings 6-1 6.2 recommended operating conditions 6-2 6.3 inputs 6-2 6.4 outputs 6-3
xiv contents copyright 1995?002 by lsi logic corporation. all rights reserved. 6.5 bidirectional pins 6-3 6.6 tolerant active negation technology electrical characteristics 6-4 6.7 pin terminations 6-7 6.8 clock timing (fastclk bit cleared) 6-8 6.9 clock timing (fastclk bit set) 6-8 6.10 reset timing 6-9 6.11 interrupt timing 6-10 6.12 register interface, nonmultiplexed pad bus 6-12 6.13 register interface, multiplexed pad bus 6-14 6.14 dma interface (nonmultiplexed mode only) 6-16 6.15 dma interface (multiplexed mode only) 6-18 6.16 burst mode dma interface (multiplexed mode) 6-20 6.17 burst mode dma interface (nonmultiplexed mode) 6-22 6.18 initiator asynchronous send timings 6-23 6.19 initiator asynchronous receive timings 6-24 6.20 target asynchronous send timings 6-25 6.21 target asynchronous receive timings 6-26 6.22 scsi-1 se transfers (5 mbytes/s) 6-28 6.23 fast scsi-2 se transfers (10 mbytes/s) 6-28 a.1 register map a-1
lsi53CF92A fast scsi controller 1-1 copyright 1995?002 by lsi logic corporation. all rights reserved. chapter 1 introduction this chapter is divided into the following sections: ? section 1.1, ?eneral description ? section 1.2, ?csi-con?ured automatically (scam) capability ? section 1.3, ?olerant technology ? section 1.4, ?eatures 1.1 general description the lsi53CF92A fast scsi controller (fsc) is a high performance cmos device designed to maximize scsi transfer rates. this device conforms to american national standards institute (ansi) standards x3.131-1986 (scsi-1) and x3.131-199x (scsi-2). the fsc includes the basic functionality of earlier scsi devices, plus additional features including fast scsi, a 24-bit transfer counter, a part-unique id code, and scsi-con?ured automatically (scam) level 1 and 2 capability. the lsi53CF92A is a second generation scsi controller that reduces protocol overhead by performing common scsi sequences in hardware, in response to a single command. the lsi53CF92A operates at sustained data transfer rates up to 10 mbytes/s in synchronous mode and 5 mbytes/s in asynchronous mode. the lsi53CF92A has on-chip 48 ma drivers for single-ended (se) transmission and is offered in a 64-pin plastic quad flat pack (pqfp) or a 64-pin thin quad flat pack (tqfp) package. the microprocessor and dma bus widths are eight bits. the fsc microprocessor bus can operate in either a multiplexed or nonmultiplexed mode, depending on the state of the mode pin. see figures 1.2 and 1.3 for more details.
1-2 introduction copyright 1995?002 by lsi logic corporation. all rights reserved. 1.2 scsi-con?ured automatically (scam) capability the lsi53CF92A differs from other members of the 53cx9x family in that scam capability has been incorporated into the device. scam requires the ability to manipulate the scsi control and data lines individually. to provide this capability, a low-level scsi programming mode has been added along with hardware assist for some scam operations. the lsi53CF92A now contains an additional register addressing mode, permitting access to two register banks, one for normal operation and one for scam operation. refer to section 2.8, ?cam capabilities, on page 2-17 , for more information. 1.3 tolerant technology the fsc features tolerant technology, which includes active negation on the scsi drivers and input signal ?tering on the scsi receivers. active negation causes the scsi req/, ack/, data, and parity signals to be actively deasserted. tolerant receiver technology improves data integrity in unreliable cabling environments, where other devices would be subject to data corruption. tolerant technology receivers ?ter the scsi bus signal to eliminate unwanted transitions without the long signal delay associated with rc-type input ?ters. this improved driver and receiver technology helps to eliminate the double clocking of data, which is the single biggest data reliability issue with scsi operations. the bene?s of tolerant technology include increased immunity to noise when the signal is going high, increased performance due to balanced duty cycles, and improved fast scsi transfer rates. tolerant technology is compatible with both the alternative one and alternative two termination schemes proposed by the ansi.
features 1-3 copyright 1995?002 by lsi logic corporation. all rights reserved. 1.4 features ? scsi-2 compatible ? ideal for target applications such as cd-roms ? up to 5 mbytes/s sustained asynchronous scsi transfer rate ? up to 10 mbytes/s sustained synchronous scsi transfer rate ? tolerant technology provides: active negation pad cells on the scsi data, parity, req/, and ack/ pins to improve fast scsi-2 performance input signal conditioning on the req/ and ack/ lines ? scam level 1 and 2 capability ? on-chip 48 ma drivers ? latch-up protection greater than 100 ma ? typical 300 mv scsi bus hysteresis ? voltage feed-through protection ? a 24-bit transfer counter that eliminates intersector transfer delays and allows single transfers up to 16 mbytes ? up to 13.3 mbytes/s dma interface ? scsi-2 tagged-queuing ? single-pin, se scsi bus operation ? combination commands implemented with on-chip sequential logic ? host intervention minimized using combination commands ? enhanced hot-plugability ? an 8-bit, split p/dma architecture ? parity generation, optional checking ? parity pass-through ? supports clock frequencies from 10 to 40 mhz ? low power cmos ? ordering information: lsi53CF92A: 64-pin pqfp or tqfp
1-4 introduction copyright 1995?002 by lsi logic corporation. all rights reserved. figure 1.1 illustrates the functional block diagram for the lsi53CF92A. figure 1.1 functional block diagram clk conversion fifo (16 x 9-bit) 24-bit transfer count destination id sync offset sync period time out read/write control parity generator and checker steering logic 24-bit counter status register interrupt register sequence step scsi control sequencer 48 ma command register dreq 9-bit 8-bit host processor rd/ wr/ cs/ dack/ a3-ale a2-dbrd/ a1 a0 dbwr/ mode reset int/ clk scsi data/control bus seq. mode seq. mode con?uration registers 1? dma bus bus transfer drivers
features 1-5 copyright 1995?002 by lsi logic corporation. all rights reserved. figure 1.2 bus con?uration, multiplexed mode (dual bus, 8-bit dma bus and 8-bit multiplexed processor address/data bus) figure 1.3 bus con?uration, nonmultiplexed mode (dual bus, 8-bit dma bus and 8-bit processor bus) lsi53CF92A dreq dack/ dbwr/ dbrd/ a1 a0 8-bit data bus dma controller 8-bit address/data bus db[7:0] dbp pad[7:0] ale rd/ wr/ cs/ mode processor with parity + 5 v lsi53CF92A dreq dack/ dbwr/ 8-bit data bus dma controller 8-bit address/data bus db[7:0] dbp pad[7:0] rd/ wr/ cs/ mode processor address bus a[3:0] with parity
1-6 introduction copyright 1995?002 by lsi logic corporation. all rights reserved.
lsi53CF92A fast scsi controller 2-1 copyright 1995?002 by lsi logic corporation. all rights reserved. chapter 2 functional description this chapter is divided into the following sections: ? section 2.1, ?ypical scsi operation ? section 2.2, ?us-initiated sequences ? section 2.3, ?arity checking and generation ? section 2.4, ?ost bus con?uration ? section 2.5, ?ma operation ? section 2.6, ?csi data transfer rates ? section 2.7, ?hip reset ? section 2.8, ?cam capabilities the fsc has a command set that allows it to perform common scsi sequences at hardware speed without host intervention. its on-chip fifo may be accessed simultaneously by the scsi bus and either the microprocessor or the host dma controller. all command, data, status, and message bytes pass through the fifo on the way to or from the scsi bus. most fsc commands have two versions: dma and non-dma. when dma instructions are used, data passes between memory and the scsi bus with the fifo acting as temporary storage when the dma channel is temporarily shut down by a higher priority event, such as dram refresh. the fifo also helps speed execution during non-dma transfers. for example, in initiator mode, the microprocessor loads the command descriptor block (cdb) and optionally, one or three message bytes into the fifo. it then issues one of several selection commands and wait for an interrupt. the fsc waits for bus free, arbitrates for the bus until it acquires it, sends the message bytes followed by the cdb, then generates an interrupt. meanwhile, a multitasking host may continue with other tasks.
2-2 functional description copyright 1995?002 by lsi logic corporation. all rights reserved. the lsi53CF92A is the newest member of the lsi53c90 family, with additional features such as fast scsi transfer rates, single-pin se scsi, 8-bit dma mode, and tolerant active negation technology. 2.1 typical scsi operation in target mode, the microprocessor enables selection and then waits for an interrupt. eventually an initiator selects the fsc. it then automatically steps through the selection and command phases before generating an interrupt. when the interrupt occurs, the entire cdb is in the fifo along with any message bytes sent by the initiator. after the selection phase has been successfully completed, the fsc may transfer bytes in any scsi information phase whether it is operating in initiator or target mode. the fsc supports disconnect/reselect in both initiator and target modes, making high performance multithreaded systems easy to implement. the fsc may transfer data phase bytes across the bus synchronously, at speeds up to 10 mbytes/s, or asynchronously, at speeds up to 5 mbytes/s. refer to section 2.6, ?csi data transfer rates, on page 2-14 , for more information. the difference between asynchronous and synchronous operation is transparent to the user except that the synchronous offset and the synchronous transfer period registers must be programmed prior to synchronous data transfer. the default, after hardware or software reset, is asynchronous transmission. data phase bytes are usually transferred using dma. the microprocessor programs an external dma controller, programs the fsc transfer count register, issues one of several fsc data transfer commands, then waits for an interrupt. the dma controller and the fsc transfer all the data without microprocessor intervention. to end the scsi transaction, the fsc target places a status byte and a message byte in the fifo. it then issues one of two single commands which causes the fsc ?st to assert status phase, send the ?st byte, assert message in phase, send the second byte, disconnect from the scsi bus (after the initiator releases ack/ [acknowledge]) and interrupt the microprocessor.
bus-initiated sequences 2-3 copyright 1995?002 by lsi logic corporation. all rights reserved. the end of a scsi transaction is similar for an fsc initiator except that it receives two bytes into its fifo. the initiator prevents the target from disconnecting by holding ack/ asserted on the bus while the microprocessor examines the status and message bytes. if both bytes are acceptable, the message accepted command instructs the fsc to release ack/, which allows the target to disconnect and causes the initiator to interrupt its host and report the disconnect. if the status and message bytes are not acceptable, the host could first issue the set atn (attention) command before issuing the message accepted command. this instructs the fsc to assert atn/ before releasing ack/, which should cause the target to request message out phase rather than disconnect. 2.2 bus-initiated sequences ? selection ? reselection ? scsi bus reset selection or reselection sequences occur in the disconnected state when the fsc is selected or reselected by another initiator or target, if the enable selection or reselection command has previously been received by the fsc. in addition to responding to bus-initiated events, the fsc may initiate a bus event by using one of several selection or reselection commands. if one of these commands starts executing, the enable selection or reselection command is cleared after another device has been selected, preventing the fsc from responding to a select or reselect command. normally the microprocessor has 250 ms (ansi recommended selection time-out period) after the chip disconnects from the bus to re-enable bus- initiated events. if the time-out period is exceeded, an initiator or target which is attempting to connect to the fsc may time-out and abort. if, on the other hand, the bus-initiated event occurs before the command starts executing, the fifo and command register is cleared and any further writes by the microprocessor are ignored until the interrupt register is read. because a selection or reselection command requires placing something in the fifo, these bytes are lost, as is any command written to the command register. the interrupt handler that services a selection or reselection command has to examine the bits in the interrupt register
2-4 functional description copyright 1995?002 by lsi logic corporation. all rights reserved. to determine if the fsc selected another device, or if it was selected by another device. the former case causes a function complete interrupt, the latter case causes a selection or reselection interrupt. 2.2.1 bus-initiated selection when the fsc has been selected as a target, the following data is in its fifo: ? bus id ? identify message ? optional two-byte command queuing message ? command descriptor block (cdb) the bus id is always present and is always one byte. it is an unencoded version of the state of the bus during selection phase. any scsi data bits that were true during selection phase are set. the target id must always be set. in arbitrating systems, the initiator id must also be set. the initiator id is optional in nonarbitrating systems. if parity checking is enabled, parity must be valid during the bus-initiated selection. if parity is not valid, the fsc does not respond to bus-initiated selection. the identify message, if sent, is also be placed in the fifo. the identify message is optional in scsi-1 systems but is always one byte if it is used. in scsi-2 systems a one or three byte message is sent, consisting of the one-byte identify message and an optional two-byte command queuing message. if the fsc is selected with atn/ false, it stores a null byte (00) in the fifo behind the bus id, then begins requesting command phase bytes. a detected parity error causes the fsc to interrupt and stop, if parity checking is enabled. if the fsc is selected with atn/ true and the scsi-2 bit is not set, it requests one message byte and places it in the fifo behind the bus id. then it requests command phase bytes unless the message byte is not a valid identify message, bit 7 in the con?uration 3 (con? 3) register is not set, or a parity error is detected, which causes the fsc to interrupt and stop. the sequence step register can then be examined to determine what events have been completed.
bus-initiated sequences 2-5 copyright 1995?002 by lsi logic corporation. all rights reserved. if the fsc is selected with atn/ true and the scsi-2 bit set, the fsc examines both the message byte and the atn/ signal to determine how many bytes to request. if the ?st byte is a valid identify message and if atn/ goes false after receiving the ?st byte, the fsc changes to command phase. if the ?st byte is a valid identify message byte (0x80?xff) and atn/ is still true, it requests two more message bytes. after requesting the message bytes, the fsc requests command phase bytes unless one of the following situations occurs: ? the ?st byte is not a valid identify message ? a parity error is detected ? atn/ goes false between the second and third bytes ? atn/ remains true but the scsi-2 bit is false. all of these conditions cause the fsc to interrupt and stop. to determine if one of these conditions has occurred, examine the sequence step register. the cdb always begins at the third or ?th byte in the fifo, assuming selection completed normally. the cdb may be 6, 10 or 12 bytes long. thus, in scsi-2, the entire fifo may be ?led if a tagged-queuing, 12-byte command is used. 2.2.2 bus-initiated reselection the fsc allows itself to be reselected as an initiator by a target if it has previously received the enable selection/reselection command. if the sequence completes normally, the fifo has the following information: ? bus id ? identify message the bus id is always present and is always one byte. it is an unencoded version of the state of the bus during reselection phase. the identify message is always present and is always one byte.
2-6 functional description copyright 1995?002 by lsi logic corporation. all rights reserved. the fsc prevents the target from disconnecting by holding ack/ asserted on the bus while the microprocessor examines the bus id and identify message bytes. the message accept command causes the fsc to release ack/. any further message bytes can be received with the transfer information command. note: the settings of the scsi-2 or queue tag enable bits do not affect this operation. 2.2.3 bus-initiated reset a scsi bus-initiated reset is recognized by the fsc at any time. when scsi rst/ pulses true, the fsc disconnects from the bus and resets its internal sequencer. if bit 6 in con?uration 1 (con? 1) register is not set, the fsc generates a scsi reset-detected interrupt. 2.2.4 stacked commands the command register is a two-deep, eight-bit read/write register that gives commands to the fsc. if dma commands are to be stacked, the transfer count must be loaded prior to loading the respective command. command stacking should only be used during data in and data out. if stacked commands are used in initiator mode, it is recommended that the features enable bit in the configuration 2 (config 2) register be set. this causes the scsi phase lines to be latched at the end of a command. 2.3 parity checking and generation the fsc has three bits that control parity generation and checking. these three bits can be accessed by the user and are described in table 2.1 . if parity checking is disabled, the fsc does not check for parity errors. in this document, the word detected in conjunction with parity error should be understood to imply that parity checking has previously been enabled. in target role, detected parity errors set the parity error bit (bit 5 in the status register) and clear the command register without causing an interrupt. in initiator role, detected parity errors set the parity error bit and, if receiving scsi bytes, assert atn/ (attention) prior to releasing
parity checking and generation 2-7 copyright 1995?002 by lsi logic corporation. all rights reserved. ack/ (acknowledge). parity errors occurring after a phase change to synchronous data in are handled differently in initiator mode. refer to chapter 5, ?ommand set, for more information on initiator commands. configuration 2 (config 2) register bit 2, the target bad parity abort bit, allows special handling for parity errors. when this bit is set, the chip aborts a receive command or receive data command if bad parity is received from the scsi bus. if a parity error occurs when the target bad parity abort bit is set, the status register parity error bit (bit 5) is set, but no additional bits are set in the interrupt or status registers after bad parity is detected. the transfer counter and fifo flags registers contain a record of how many bytes were transferred before the command was aborted. for additional information on the parity bits, refer to chapter 4, ?egisters. the lsi53CF92A has one parity pin (dbp). in both the multiplexed bus configuration mode and in the nonmultiplexed bus configuration mode, the processor connects to the fifo on an 8-bit bus only. in both of these modes, the internal parity generator creates parity to send to the scsi bus. when the dbp pin is enabled, parity may pass between the scsi and host dma bus without change or may be generated by the fsc from the data byte. whether generated internally or externally, the parity bit is always loaded into the fifo along with the data byte. from there on, it moves through the fifo along with the data byte. the fifo may be accessed by three buses: scsi bus, microprocessor bus, or host dma bus. table 2.1 parity control control bit data direction bit set bit not set parity checking, con?uration 1 (con? 1) , bit 4 scsi to fifo enable parity checking and error reporting. sdp loaded into fifo. disable parity checking and error reporting. parity generator to fifo. test parity, con?uration 1 (con? 1) , bit 5 fifo to scsi fifo to memory sdp is a replica of sd7. dbp is a replica of db7. fifo to sdp. fifo to dbp. dma parity, con?uration 2 (con? 2) , bit 0 dack/ to fifo fifo to scsi dbp to fifo. enable parity checking and error reporting. parity generator to fifo. disable parity checking and error reporting.
2-8 functional description copyright 1995?002 by lsi logic corporation. all rights reserved. if parity test mode is enabled during a dma transfer, dbp is a duplicate of db7. this is true both for data flowing from the fifo to the scsi data bus (sdb) pins or data flowing from the fifo to the host data bus (db) pins. the fsc ?gs parity errors as data comes into the fifo from the scsi bus, or as it leaves the fifo on its way out to the scsi bus. 2.4 host bus con?uration the dma and microprocessor buses may be con?ured in one of the two following ways. 2.4.1 mode description the operating mode is selected by the mode strapping pin; refer to chapter 3, ?ignal descriptions, for the setting of either mode. the two operating modes are labeled multiplexed mode and nonmultiplexed mode. refer to chapter 1, ?ntroduction, figure 1.2, and figure 1.3 for con?uration diagrams. both of these dual bus modes have separate data buses for dma and microprocessor, which may be active simultaneously provided cs/ is not accessing the fifo. 2.4.2 multiplexed bus con?uration mode in this dual-bus mode, 8-bit operations are supported by the dma data bus. the microprocessor interface is supported by the pad bus. fifo parity is not available for data transfers over the pad bus. the direction of transfer is determined by the rd/ and wr/ lines. cs/ must be active during pad bus accesses. in the multiplexed bus configuration mode, register addresses and register data are multiplexed on the pad bus. the register address on the pad[3:0] lines is latched into the chip on the high to low transition of ale (a3). in this bus con?uration mode, the data bus con?uration is for 8-bit dma transfers. pin a2 functions as the data bus read signal (dbrd/), which drives the dma read data. a1 and a0 must be tied to ground. multiplexed dual bus; 8-bit dma bus and 8-bit multiplexed processor address/data bus. nonmultiplexed dual bus; 8-bit dma bus and 8-bit nonmultiplexed processor bus.
dma operation 2-9 copyright 1995?002 by lsi logic corporation. all rights reserved. 2.4.3 nonmultiplexed bus con?uration mode like the multiplexed bus con?uration mode, this dual bus mode is con?ured for 8-bit transfers. in this dual bus mode interface, dma operations are supported by the db bus, and the microprocessor interface is supported by the pad bus. fifo parity is not available for data transfers over the pad bus. the direction of transfer is determined by the rd/ and wr/ lines. cs/ must be active during pad bus accesses. in the nonmultiplexed bus configuration mode, transfers occur on the microprocessor interface over the pad bus, which operates as a nonmultiplexed data only bus. the register address is carried by the a[3:0] lines and is latched into the chip on the high to low transition of cs/. 2.5 dma operation the fsc supports 8-bit dma transfers. the on-chip fifo allows the fsc to support normal and burst mode transfers. the dma interface protocol runs asynchronous to the chip clock. the dma request signal (dreq) is asserted when the dma is ready for a transfer to or from the dma channel. dreq is asserted only when the dma acknowledge signal (dack/) is inactive, and is released on the leading edge of dack/. dreq remains asserted until the chip receives as many dack/s as it needs or can handle. 2.5.1 dma threshold the threshold is the number of bytes in the fifo that trigger dreq. for dma read, dreq is asserted when the fifo contains at least the threshold number of bytes. for dma write, the fifo must be able to accept this number of bytes. for 8-bit dma operation the normal threshold is one byte. 2.5.2 normal dma mode in normal operation, dreq remains true until the fifo empties or fills, depending on the direction of the transfer. figure 2.1 illustrates the case where the threshold is always exceeded. this is typical of a dma interface that is slower than the scsi device to which the system is connected.
2-10 functional description copyright 1995?002 by lsi logic corporation. all rights reserved. normal dma mode tends to monopolize the dma bus, and slows the entire system down to the performance level of the scsi device to which the chip is connected. in single-threaded systems, however, this remains the most ef?ient method of transferring data as long as important events, like dram refresh, can interrupt the dma transfer. figure 2.1 normal dma mode 2.5.3 threshold eight mode threshold eight mode causes the fsc to wait until eight bytes or more can be transferred before it requests service from the external dma controller. because the dma bus can operate at speeds ?e to ten times greater than typical scsi devices, this mode allows scsi operations to run effectively in parallel with other processes. the threshold eight bit in con?uration 3 (con? 3) register changes the threshold to eight bytes. refer to the description for the con?uration 3 (con? 3) register in chapter 4, ?egisters. threshold eight mode is enabled by setting bit 0 in the con?uration 3 (con? 3) register and is valid in both bus con?urations. threshold eight mode operates only during scsi data in or data out phase. note: when enabling this mode, the synchronous data offset can only be set to seven or less. threshold eight mode causes dreq to remain false until the fifo can accommodate an eight-byte transfer. this improves dma bus ef?iency by keeping the chip off this bus until it can transfer at least eight bytes. with threshold eight enabled, the chip retains control of the dma channel as long as one transfer can be accommodated. the transfer continues in normal mode whenever the transfer counter drops below eight bytes and the threshold drops to one transfer. dreq dbrd/ or dbwr/ dack/
dma operation 2-11 copyright 1995?002 by lsi logic corporation. all rights reserved. the following conditions must be true for a dma threshold eight transfer to occur: ? threshold eight mode is enabled. ? transfer counter indicates eight or more bytes. ? the fifo can accommodate an 8-byte transfer as follows: the fifo contains at least eight bytes of data to transfer to memory, or at least the top eight bytes of the fifo are empty to receive the eight-byte transfer from memory. because the threshold eight mode is enabled during dma burst mode, the dma burst is limited to eight transfers. this feature forces the chip to periodically relinquish control of the dma channel, allowing other devices to gain access to the bus to perform such operations as memory refresh. 2.5.4 dma burst mode burst mode, or alternate dma mode, is a special mode devised to maximize data throughput using most dma controllers. dma burst mode is enabled by setting both the threshold eight and the alternate dma mode bits in the con?uration 3 (con? 3) register. threshold eight causes the fsc to delay assertion of dreq until it can transfer eight bytes. alternate dma mode causes the fsc to deassert dreq after the byte transfers, causing the dma controller to relinquish the bus. this regular surrendering of the dma channel has bene?s for two common dma interface problems. for dma controllers that do not recognize higher priority requests until the current device ?ishes, the fsc can periodically force dma arbitration. this allows dram refresh and other operations to occur during scsi operations. for dma controllers that are much faster than the scsi host or peripheral to which the system is connected, bus ef?iency is improved by ensuring that the fsc has data to transfer while the dma controller is controlling the bus. dma burst mode can be enabled in both bus con?urations. dma burst mode affects the deassertion of dreq and assertion of dack/ for dma reads and writes.
2-12 functional description copyright 1995?002 by lsi logic corporation. all rights reserved. in the multiplexed bus con?uration mode, the fsc is designed to operate with a dma controller that has timings similar to an 8237. because many systems use one of the 8237 channels for dram refresh and because the 8237 does not recognize a higher priority request until it ?ishes its current transfer, burst mode gives the best transfer rate without sacri?ing memory integrity. 2.5.4.1 deassertion of dreq the fsc remains in burst mode as long as more than eight bytes remain to be transferred. however, if the transfer counter drops below eight, then the fsc switches out of burst mode for the last one to seven bytes. the last bytes are transferred in normal dma mode where dreq goes true and stays true as long as the fifo is able to transfer data; dack/ cycles true then false for each transfer. because dack/ must cycle true then false for every dma transfer in this mode, normal mode is sometimes referred to as single transfer mode. ? single transfer mode : dreq goes true and stays true as long as the fifo is able to transfer data. dack/ cycles true then false for every transfer. ? multiple dma transfers per dreq : in the multiplexed bus con?uration mode, dreq is deasserted after the trailing edge of dbwr/ or dbrd/. dack/ remains asserted throughout multiple transfers. in the nonmultiplexed bus con?uration mode, dreq is deasserted after the trailing edge of dack/ of the next-to-last dma transfer. in the nonmultiplexed bus con?uration mode, dack/ toggles for each dma read cycle. 2.5.4.2 dma read when dma burst mode is enabled, the method by which dma read data is transferred to the system bus depends on the bus con?uration mode. the dma read data is enabled onto the db bus by dack/ and either the rd/ or dbrd/ input signal, as follows.
dma operation 2-13 copyright 1995?002 by lsi logic corporation. all rights reserved. ? multiplexed bus con?uration mode : data is enabled when both dbrd/ and dack/ are true. for multiple dma transfers, dack/ remains asserted throughout the multiple transfers and dbrd/ toggles for each transfer. ? nonmultiplexed bus con?uration mode : data is enabled when dack/ is true. dack/ toggles for each dma transfer. 2.5.4.3 dma write in dma burst mode, the functionality of dack/ and dbwr/ is unchanged for single dma transfers per dreq. for multiple dma transfers per dreq, dack/ remains asserted throughout the multiple transfers and dbwr/ toggles for each transfer. figure 2.2 illustrates the dma burst mode, multiplexed mode and nonmultiplexed mode writes. figure 2.2 dma burst mode (multiplexed mode and nonmultiplexed mode writes) figure 2.3 illustrates the dma burst mode, nonmultiplexed mode reads. figure 2.3 dma burst mode (nonmultiplexed mode reads) 2.5.5 single-pin, se scsi the lsi53CF92A improves fast, se scsi performance by reducing capacitance of the scsi input and output signals. single pin scsi provides the best performance for fast, se scsi, and reduces signal attenuation at scsi-1 transfer rates. dreq dack/ dbrd/ or dbwr/ dreq dack/
2-14 functional description copyright 1995?002 by lsi logic corporation. all rights reserved. 2.6 scsi data transfer rates performance numbers for the fsc are based on se connection to the scsi bus with no external transceivers. 2.6.1 asynchronous operation the asynchronous transmission rate varies with cable length and the clk period. the fsc can reach sustained transfer rates of 5 mbytes/s on short (1 foot) cables using typical devices operating at or near nominal voltage and temperature. the typical transfer rate on a 6-meter cable is 4 mbytes/s using two typical fscs talking to each other. the worst case asynchronous transmission rate, over voltage, temperature, and process variations is 3 mbytes/s on a maximum length (6 meters), se cable and 4 mbytes/s on a 1-foot cable. the asynchronous transmission rate is only slightly affected by the clk frequency when sending data. the fsc drives the data bus for a minimum of one clk period (plus any additional time required to meet the ansi required 55 ns setup time) before asserting req/ or ack/. the clk frequency does not affect the asynchronous transfer rate when receiving data. when the enable active negation bit is set, con?uration 4 (con? 4) bit 2, the lsi53CF92A can transfer data asynchronously at up to 5 mbytes/s. 2.6.2 synchronous operation the synchronous data transmission period is equal to the clk input frequency multiplied by the encoded value in the synchronous transfer period register. sustained synchronous transfer rates of 10 mbytes/s are attainable across the commercial voltage and temperature range. the lsi53CF92A can transfer synchronous scsi data in both initiator and target modes at transfer rates up to 10 mbytes/s, using an input clock frequency of 40 mhz. the scsi-1 and fast scsi-2 minimum timing requirements are in table 2.2 .
chip reset 2-15 copyright 1995?002 by lsi logic corporation. all rights reserved. to support maximum fast scsi transfer rates and scsi-1 transfer requirements, the fastscsi (bit 4) and fastclk (bit 3) bits have been added to the con?uration 3 (con? 3) register. they modify the scsi state machine to provide fast and normal synchronous timings depending upon the clock frequency. a full description of the operations of these bits and the required clock frequencies are provided in the con?uration 3 (con? 3) register description in chapter 4, ?egisters. during synchronous scsi transfers, the assertion and deassertion of the req/ and ack/ signals is programmable using the fastclk bit and other bits in the synchronous offset register. the input clock duty cycle affects the half clock assertion/deassertion delays. for more information, see the synchronous offset register description in chapter 4, ?egisters. 2.7 chip reset the fsc has the following three levels of reset: ? hard ? soft ? disconnect 2.7.1 hard reset a hard reset is executed, when using the reset chip command, or when the reset pin is asserted by external hardware. it stops all chip operations, resets all functions in the chip, and returns the chip to a disconnected state. the reset chip command remains at the top of the command register fifo, which locks the chip and all registers in a reset state until a nop command is issued. at power up, the reset pin must be asserted as v dd ?st becomes stable. table 2.2 minimum timing requirements mode setup hold assert/negate scsi-1 55 ns 100 ns 90 ns se fast scsi-2 25 ns 35 ns 30 ns
2-16 functional description copyright 1995?002 by lsi logic corporation. all rights reserved. 2.7.2 soft reset a soft reset is applied when the scsi bus reset condition is received through the rst/ pin, or when the reset scsi bus command is issued, which asserts the rst/ pin. this condition resets the following subset of the functions reset by the hard reset: ? resets dma interface ? resets bus-initiated selection/reselection module ? resets command sequence module ? resets sequence step and clears sequencer mode bits (enable select/reselect = 0, target = 0, initiator = 0) ? initializes command register fifo to empty ? releases all scsi signals except rst/ ? resets disconnect, initiator, and target command modules the reset scsi bus command causes the rst/ signal to be asserted. see chapter 5, ?ommand set, for further description of this command. a scsi bus reset may occur in any mode. the rst/ signal is asserted by another scsi device on the bus, and returns the chip to a disconnected state. the chip generates a scsi reset interrupt to the microprocessor if the interrupt is not disabled by bit 6 of the con?uration 1 (con? 1) register. if the scsi bus reset is still active when the microprocessor clears the interrupt, a new interrupt is generated. this new interrupt must be serviced. the reset scsi bus command asserts the scsi rst/ pin for approximately 25 s and returns the chip to disconnected status. a scsi reset interrupt is generated if the interrupt is not disabled by bit 6 of the con?uration 1 (con? 1) register.
scam capabilities 2-17 copyright 1995?002 by lsi logic corporation. all rights reserved. 2.7.3 disconnect reset the disconnect reset is caused by various circumstances that result in the chip becoming disconnected from the scsi bus, as follows: ? the target mode disconnect, disconnect sequence, or terminate sequence command is issued to the chip. ? the chip is in initiator mode and the scsi bus changes to the bus free state. ? the select or reselect command terminates with a selection time-out. a disconnect reset resets the following subset of the functions reset by the soft reset: ? sequencer mode bits are cleared (target = 0 and initiator = 0). ? initializes command register fifo to empty. ? releases all scsi signals except rst/. ? resets disconnect, initiator, and target command modules. 2.8 scam capabilities this section de?es how scam functionality is accommodated within the lsi53CF92A scsi protocol chip. the scam terminology and functionality presented within this section is consistent with de?itions provided within the scam speci?ation x3t9.2/93-109r5. the scam additions to the lsi53CF92A allow the chip to be a level 1 or level 2 scam master or slave device. to provide scam functionality, scsi interface chips must be able to control individual scsi control and data lines and be able to disable active negation of signals. the lsi53CF92A uses hardware sequencers to control all scsi interface activity. the general strategy for scam implementation in the lsi53CF92A is to provide a low-level scsi programming mode along with hardware support for some of the scam operations.
2-18 functional description copyright 1995?002 by lsi logic corporation. all rights reserved. 2.8.1 scsi low-level programming the lsi53CF92A design provides scam capability with a generic low-level scsi programming mode. low-level access to the scsi bus is controlled by the low level bit, scsi control (scontrol) register, bit 0. when the low level bit is set, all scsi bus sequences are performed using software control. arbitration may be performed purely in software or by using the arb bit, scsi control (scontrol) register, bit 1. see section 2.8.2, ?cam operations, , for details. during low-level operation, no relational restrictions exist between scsi signals; data bits may be driven without respect to the i/o control line, and there is no distinction between target/initiator signals. 2.8.2 scam operations the following categories describe the different scam operations: ? section 2.8.2.1, ?rbitration with or without an id ? section 2.8.2.2, ?cam selection ? section 2.8.2.3, ?esponse to scam selection ? section 2.8.2.4, ?esponse to normal selection ? section 2.8.2.5, ?cam protocol and transfer cycles ? section 2.8.2.6, ?imitations 2.8.2.1 arbitration with or without an id arbitration with or without an id is possible through low-level control by utilizing the scsi output data latch and the arb bit, scsi control (scontrol) register, bit 1. during arbitration, the contents of the scsi output data latch (sodl) are asserted onto the scsi bus in a direct bit-mapped fashion. during arbitration, legal values for the scsi output data latch (sodl) are {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80}. arbitration without an id is accomplished by setting the sodl to {0x00} prior to the start of arbitration. the following steps should be performed by software to arbitrate for the scsi bus in low-level mode: step 1. set the low level bit in the scsi control register. step 2. write bit-mapped id (normal arbitration) or 00 (no id) to the scsi output data latch (sodl) register.
scam capabilities 2-19 copyright 1995?002 by lsi logic corporation. all rights reserved. step 3. set the arb bit. step 4. wait for the arb1 status bit (normal arbitration) or the arb4 status bit (scam, no id). examine the bus (read scsi bus data lines (sbdl) ) if (any device with higher id is present) then another device has won arbitration turn off arb and low level goto step 1 else arbitration has been won assert bsy, sel using socl register turn off arb bit endif note: if another device wins arbitration and asserts sel/, the fsc deasserts bsy/ and rearbitrates the next time a bus free condition is detected. the fsc continues arbitrating until either it wins (arb1, arb4 set and no higher ids on the bus) or until the arb bit is reset. 2.8.2.2 scam selection after arbitration is complete as described in section 2.8.2.1 , bsy/ and sel/ are asserted on the bus. the following steps should be performed by software to generate a scam selection: step 1. assert msg/ using the scsi output control latch (socl) register. step 2. delay at least two de-skew delays, then release bsy/ using the scsi output control latch (socl) register. step 3. maintain sel/ and msg/ asserted with bsy/ released for a minimum of a scam selection response time, then release msg/. note: the scam speci?ation provides for two distinctly different scam selection response times; the long scam selection response time (250 ms), and the short scam selection response time (1 ms). many level 2 scam systems can accommodate the 1 ms scam selection response time. step 4. wait until msg/ has been released by all other devices (examine the scsi bus control lines (sbcl) register), using wired-or glitch ?tering in software.
2-20 functional description copyright 1995?002 by lsi logic corporation. all rights reserved. step 5. assert bsy/ using the scsi output data latch (sodl) register. step 6. wait two de-skew delays. step 7. assert sel/ and i/o while maintaining bsy/ asserted. at this time, if the device is a scam master, c/d should also be asserted. step 8. assert db6 and db7 by ?st writing them in the scsi output data latch (sodl) register, then enabling their drivers with bit 2 of the scsi control (scontrol) register. step 9. wait two de-skew delays. step 10. release sel/ and wait until sel/ has been deasserted, using wired-or glitch ?tering in software. step 11. release db6 and examine the scsi bus signals. if c/d is not asserted, then there are no scam master devices participating, and the slave devices release all signals. if c/d is asserted, wait for db6 to be released by all devices, using wired-or glitch ?tering, then assert sel/. this completes initiation of the scam selection protocol. 2.8.2.3 response to scam selection when response to scam selection is enabled (enss bit set in the scsi control (scontrol) register), the fsc monitors the scsi bus for scam selection attempts (sel/ and msg/ asserted when bsy/ released). upon detection of a scam selection, the fsc responds by asserting sel/ and msg/, and then interrupting the processor. a scam selection interrupt is indicated when both bits 1 and 0 of the interrupt register are set (normally mutually exclusive events). following a scam selection interrupt, software must enter the low-level programming mode and participate in the scam protocol. the following minimal steps must be taken by software in preparation for and response to the scam selection interrupt: step 1. in the scsi control (scontrol) set the enss (bit 3) and low level (bit 0). step 2. wait for scam selection interrupt. step 3. in the scsi output control latch (socl) set msg (bit 2). step 4. in the scsi control (scontrol) register reset enss (bit 3). step 5. release msg/.
scam capabilities 2-21 copyright 1995?002 by lsi logic corporation. all rights reserved. step 6. wait until msg/ has been released by all other devices (examine the scsi bus control lines (sbcl) register), using wired-or glitch ?tering in software. step 7. assert bsy/ using the scsi output data latch (sodl) register. step 8. wait two de-skew delays. step 9. assert sel/ and i/o while maintaining bsy/ asserted. at this time, if the device is a scam master, c/d should also be asserted. step 10. assert db6 and db7 by ?st writing them in the scsi output data latch (sodl) register, then enabling their drivers with bit 2 of the scsi control (scontrol) register. step 11. wait two de-skew delays. step 12. release sel/ and wait until sel/ has been deasserted, using wired-or glitch ?tering in software. step 13. release db6 and examine the scsi bus signals. if c/d is not asserted, then there are no scam master devices participating, and the slave devices releases all signals. if c/d is asserted, wait for db6 to be released by all devices, using wired-or glitch ?tering, then assert sel/. this completes initiation of the protocol for response to scam selection. 2.8.2.4 response to normal selection the response to normal selection attempts is determined by the state of the endr bit (bit 4 in the scsi control (scontrol) register). scam slave devices with uncon?med default ids may not respond to selection until a scam default id selection response time period elapses. setting the endr bit causes the fsc to delay its response to selection, using the select/reselect time-out register to control the delay period. after the delay period elapses, the fsc responds by asserting bsy/ and continues to process the selection as described elsewhere in this technical manual. when this bit is cleared, the fsc responds to normal selection attempts as soon as it detects that it is being selected (within a scam-tolerant selection response time).
2-22 functional description copyright 1995?002 by lsi logic corporation. all rights reserved. 2.8.2.5 scam protocol and transfer cycles the scam protocol functions through a sequence of transfer cycles. during each cycle, certain devices send data to all participating scam devices. the actual data received is the logical-or of the data sent by all sending devices. each transfer cycle is fully interlocked in the same sense that asynchronous data transfers are interlocked. completion of each step of the transfer is explicitly acknowledged, and the transfer rate adapts automatically to the speed of the nodes involved. transfer cycles use db[7:5] as handshake lines and db[4:0] as data lines. at the beginning and end of each cycle, db7 is asserted while db6 and db5 are released. each device sequences through the following steps for each transfer cycle: step 1. use the scsi output data latch (sodl) register to place data on db[4:0], if the device is sending data, and assert db5. use bit 2 of the scsi control (scontrol) register to drive the data onto the scsi bus. step 2. release db7 using the scsi output data latch (sodl) register. step 3. wait until db7 is released by all other devices (examine the scsi bus data lines (sbdl) register), using wired-or glitch ?tering in software. step 4. read and latch data from db[4:0], and assert db6. step 5. release db5. step 6. wait until db5 is released by all other devices, using wired-or glitch ?tering in software. step 7. release or change db[4:0], and assert db7. step 8. release db6. step 9. wait until db6 is released by all other devices, using wired-or glitch ?tering in software.
scam capabilities 2-23 copyright 1995?002 by lsi logic corporation. all rights reserved. figure 2.4 illustrates the scam transfer cycles. figure 2.4 scam transfer cycles the scam protocol continues through successive transfer cycles until the master device(s) choose to terminate it by releasing c/d and all other signals. slave devices notes the release of c/d and release all other signals. 2.8.2.6 limitations low-level mode allows independent control of all scsi bus signals with the following two limitations: ? the scsi reset signal cannot be directly controlled using low-level mode; however, the reset scsi bus command may be issued during low-level mode, which asserts scsi reset as described in section 2.7.2, ?oft reset, on page 2-16 . ? the scsi parity signal cannot be directly controlled using low-level mode; however, when the assert data bus (adb) bit is set, the fsc generates parity for the scsi bus using the low level parity control (lpc) bit to select even or odd parity. 1234567 db5 db[0:4] 89 db6 db7 step note: signals are shown asserted low. valid data latched
2-24 functional description copyright 1995?002 by lsi logic corporation. all rights reserved.
lsi53CF92A fast scsi controller 3-1 copyright 1995?002 by lsi logic corporation. all rights reserved. chapter 3 signal descriptions this chapter contains signal descriptions and pin diagrams for the 64-pin pqfp and the 64-pin tqfp packages. a slash (/) indicates an active low signal; b = bidirectional signal; i = input signal; and o = output signal. figure 3.1 is the functional signal grouping and figure 3.2 is the pin con?uration for the chip. figure 3.1 functional signal grouping int/ a3-ale a2-dbrd/ a1* a0* cs/ rd/ wr/ pad[7:0] dreq dack/ dbwr/ db[7:0], dbp clk reset mode lsi53CF92A microprocessor and dma interface rst/ bsy/ sel/ req/ ack/ atn/ msg/ cd/ io/ sd[7:0] sdp scsi control miscellaneous power and con?uration scsi data vdd vss note: * in multiplexed mode, these two pins must be tied to vss. see the signal description on page 3-2 for details.
3-2 signal descriptions copyright 1995?002 by lsi logic corporation. all rights reserved. table 3.1 lists the microprocessor and dma interface signals group. table 3.1 microprocessor and dma interface signals name bump type description pad[7:0] 63?0 58?5 b bidirectional, active high processor address-data bus with internal 200 a pull-ups. these pins allow the processor to access the internal registers of the chip at the same time the dma bus is active. in multiplexed mode, address and data share this bus. in nonmultiplexed mode, these pins are for data only. db[7:0] 15?4 12?0 8-6 b bidirectional, active high data bus with internal 200 a pull-ups. these pins are the 8-bit dma data bus. dbp 16 b odd parity for db[7:0]. a0 a1 a2-dbrd/ a3-ale 49 50 52 53 i in nonmultiplexed mode, these ttl-compatible inputs are address bits [3:0]. in multiplexed mode, they become a0, a1, dbrd/, and ale. the address on the pad bus is internally latched when ale switches from high to low. dbrd/ is the read signal for the db bus. also, in multiplexed mode, a1 and a0 must be tied to v ss to transfer data on db[7:0]. dbwr/ 4 i active low, dma write signal which strobes db[7:0] data into the fifo when dack/ is true. cs/ 47 i active low chip select. this ttl-compatible input enables eight-bit access to internal registers during read or write. cs/ uses the address inputs to access any register (including the flfo) while dack/ accesses only the fifo. cs/ and dack/ may both be true at the same time, provided that cs/ is not accessing the fifo. rd/ 46 i active low register read signal. this ttl-compatible input allows internal registers to drive the data bus when cs/ is also true.
3-3 copyright 1995?002 by lsi logic corporation. all rights reserved. wr/ 45 i active low register write signal. this ttl- compatible input causes the fsc to write data into its internal registers when cs/ is also true. int/ 42 o active low, open drain interrupt signal to the microprocessor. it is asserted on the rising edge of clk. it may be cleared by reading the interrupt register, by a host hardware reset, or the reset command (but not by a scsi reset). this output cannot be masked by the user. an external pull-up is required. see figure b.1 for details. dreq 2 o 3-state, active high dma request signal to the dma controller. dreq remains true as long as the fifo either: ? contains at least one byte to send to memory dma read, ? has room for one more byte during dma write. if threshold eight mode is enabled, dreq is not asserted until the fifo can accommodate an eight-byte transfer. when the testin/ pin is enabled, dreq is the output of the ?nd tree (see the testin/ pin description on page 3-5 ). dack/ 3 i active low dma acknowledge from the dma controller. dack/ accesses the fifo only, while cs/ accesses any register, including the fifo. clk 48 i square wave clock input that generates internal chip timing. the maximum frequency is 40 mhz. the minimum frequency for asynchronous scsi is 10 mhz. the minimum frequency for synchronous scsi is 12 mhz. the synchronous transmission period is equal to the clk period multiplied by the value in the synchronous transfer period register. the asynchronous transmission rate is indirectly affected by the clk period. reset 44 i active high chip reset. reset must be asserted for at least two clk periods after the voltage on the power pins has reached minimum vdd. table 3.1 microprocessor and dma interface signals (cont.) name bump type description
3-4 signal descriptions copyright 1995?002 by lsi logic corporation. all rights reserved. table 3.2 lists the scsi signals group. table 3.2 scsi signals name bump type description sd[7:0] sdp 27, 25?2, 20?8 28 b 48 ma, scsi data/parity output bus. these pins are active low scsi data signals. these signals are actively deasserted when active negation is enabled and the chip is active on the scsi bus; otherwise, these are open drain scsi outputs. sel/, bsy/, rst/ 35 30 33 b 48 ma, open drain scsi i/os, active low. the reset scsi bus command that causes the fsc to drive rst/ true for 25?0 s, depending on the clk frequency and clock conversion factor. req/ 38 b 48 ma, scsi i/o. asserted only in target mode. this signal is actively deasserted when active negation is enabled and the chip is active as a target on the scsi bus; otherwise, this is an open drain scsi output. ack/ 32 b 48 ma, scsi i/o. driven by the fsc in initiator mode only. this signal is actively deasserted when active negation is enabled and the chip is active as an initiator on the scsi bus; otherwise, this is an open drain scsi output. atn/ 29 b 48 ma, open drain output, schmitt trigger input. in initiator mode it is an output, and is automatically asserted when the fsc detects an incoming parity error, or may be asserted by certain fsc commands. in target mode, this signal is an input. msg/, cd/, io/ 34 37 39 b scsi phase signals. they are 48 ma outputs in target mode, and schmitt trigger inputs in initiator mode.
3-5 copyright 1995?002 by lsi logic corporation. all rights reserved. table 3.3 lists the con?uration and test signals group. table 3.4 lists the power and ground signals group. table 3.3 con?uration and test signals name bump type description mode 41 i this ttl-compatible input pin con?ures the pad bus and the address control bus (a3-ale, a2-dbrd/, a1, a0) for multiplexed bus operation when low, and for nonmultiplexed bus operation when high. testin/ 54 i test in. when this pin is driven low, the lsi53CF92A connects all inputs and outputs to an ?nd tree. the scsi control signals and data lines are not connected to the ?nd tree. the output of the ?nd tree is connected to the dreq pin. this allows the user to verify chip connectivity to the board and to determine exactly which pins are not properly attached. when the testin/ input is driven low, internal pull-ups are enabled on all input, output, and bidirectional pins, all output and bidirectional signals are high impedance, and the dreq pin is enabled. connectivity can be tested by driving one of the lsi53CF92A pins low. the dreq pin should respond by driving low. table 3.4 power and ground signals name bump description vdd-core 5, 40 +5 v power input. vdd-db and scsi 17 n/a vdd-pad 64 n/a vss-core 1, 43, 51 ground. lsi logic recommends using a ground plane. vss-scsi 21, 26, 31, 36 n/a vss-db 9, 13 n/a vss-pad 59 n/a
3-6 signal descriptions copyright 1995?002 by lsi logic corporation. all rights reserved. figure 3.2 lsi53CF92A 64-pin plastic qfp and thin qfp pin con?uration 1 vss dreq dack/ dbwr/ vdd db0 db1 db2 vss db3 db4 db5 vss db6 db7 dbp vdd pad7 pad6 pad5 pad4 vss pad3 pad2 pad1 pad0 testin/ a3-ale a2-dbrd/ vss a1 a0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk cs/ rd/ wr/ reset vss int/ mode vdd io/ req/ cd/ vss sel/ msg/ rst/ lsi53CF92A 64-pin pqfp/tqfp vdd sd0 sd1 sd2 vss sd3 sd4 sd5 sd6 vss sd7 sdp atn/ bsy/ vss ack/ 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1. see figure 6.27 and figure 6.28 .
lsi53CF92A fast scsi controller 4-1 copyright 1995?002 by lsi logic corporation. all rights reserved. chapter 4 registers this chapter contains descriptions of all fsc registers. a register map is provided in appendix a, ?egister map. all register values are given in hexadecimal. the terms set and assert refer to bits that are programmed to binary one. similarly, the terms reset, clear, or deassert refer to bits that are programmed to binary zero. some fsc registers have different meanings during reads than writes. when cs/ is true, the register being accessed is determined by either rd/ or wr/ together with the address pins a[3:0] and the state of the register bank select bit (bit 3 in the con?uration 4 (con? 4) register). the fifo may be accessed using either cs/ or dack/ together with rd/ or wr/. address pins a[3:0] are ignored when dack/ is active, but must be driven when cs/ is active. the fsc registers must not be read while they are in transition, especially the fifo , fifo flags , and transfer counter registers. this chapter contains the following sections: ? section 4.1, ?tandard register set ? section 4.2, ?cam register set
4-2 registers copyright 1995?002 by lsi logic corporation. all rights reserved. reserved bits should be masked when read. all register bits in the lsi53CF92A are cleared to zero after a hard reset, except as noted in table 4.1 . the shaded area in table 4.2 contains the scam register set. table 4.1 register reset values register bit(s) reset value transfer count all indeterminate transfer counter high/id register all 10010100 destination bus id [2:0] indeterminate status [2:0] indeterminate clock conversion factor [2:0] 010 synchronous transfer period [4:0] 00101
4-3 copyright 1995?002 by lsi logic corporation. all rights reserved. table 4.2 register set register address con?uration register 4, bit 3 = 0 con?uration register 4, bit 3 = 1 register bank 0 read register bank 0 write register bank 1 read register bank 1 write 0x00 transfer counter low transfer counter low transfer counter low transfer counter low 0x01 transfer counter middle transfer counter middle transfer counter middle transfer counter middle 0x02 fifo fifo fifo fifo 0x03 command command command command 0x04 status destination bus id status destination bus id 0x05 interrupt time-out interrupt time-out 0x06 sequence step synchronous transfer period sequence step synchronous transfer period 0x07 fifo flags synchronous offset fifo flags synchronous offset 0x08 con?uration 1 (con? 1) con?uration 1 (con? 1) scsi control (scontrol) scsi control (scontrol) 0x09 reserved clock conversion scsi status (sstatus) reserved 0x0a reserved test scsi output control latch (socl) scsi output control latch (socl) 0x0b con?uration 2 (con? 2) con?uration 2 (con? 2) scsi bus control lines (sbcl) reserved 0x0c con?uration 3 (con? 3) con?uration 3 (con? 3) reserved reserved 0x0d con?uration 4 (con? 4) con?uration 4 (con? 4) con?uration 4 (con? 4) con?uration 4 (con? 4) 0x0e transfer counter high/id transfer counter high/id scsi output data latch (sodl) scsi output data latch (sodl) 0x0f reserved reserved scsi bus data lines (sbdl) reserved
4-4 registers copyright 1995?002 by lsi logic corporation. all rights reserved. 4.1 standard register set the standard register set can be accessed when cs/ is true. the speci? register being accessed is determined by the states of the rd/ and wr/ signals together with the address pins a[3:0]. the state of bit 3 of con?uration 4 (con? 4) selects between two banks of registers. registers 0x00 through 0x07 of the standard register set are accessible with either register bank setting. registers 0x08 through 0x0f of the standard register set are accessible when bank 0 is selected, and the scam register set is accessible in registers 0x08 through 0x0f when register bank 1 is selected. the complete register map, including scam registers, is shown in table 4.2 on page 4-3 . register: 0x00?x01 transfer counter write only register bank 0 or 1 these two registers, together with the transfer counter high/id register (0x0e), form a 24-bit register which stores the transfer count value for dma operations. they specify the number of bytes that are to be transferred over the scsi bus. values written to these two registers are stored internally and loaded into the transfer count by any dma command. these values remain unchanged while the transfer counter decrements. thus, successive blocks of equal size may be transferred without reprogramming the count. they may be reprogrammed any time after the previous dma operation has started, whether it has ?ished or not. when the features enable bit is clear (which disables the transfer counter high/id register), a zero value in registers 00 and 01 speci?s a maximum length count of 64 kbytes. when the features enable bit is set, and the transfer counter high/id register is enabled, zeros specify a maximum length count of 16 mbytes. these registers are not changed by any reset. their states are unpredictable after power-up. 76543210 default xxxxxxxx
standard register set 4-5 copyright 1995?002 by lsi logic corporation. all rights reserved. register: 0x00?x01 transfer counter read only register bank 0 or 1 these registers combine with the transfer counter high/id register (0x0e) to form a 24-bit transfer counter. a read from these addresses returns the value currently in the counter. dma commands use the counter to terminate a transfer. when the counter decrements to zero, the terminal count bit in the status register is set, indicating the current transfer is complete. any dma command loads the transfer count into the counter. a dma nop (0x80) loads the counter while the non-dma nop (0x00) does not. during scsi data phases, the transfer counter decrements on the leading edge of the following: ? target decremented by data in phase dack/ * data out phase req/ ? initiator decremented by synchronous data in dack/ * asynchronous data in ack/ data out dack/ * ? target decremented by message in, status dack/ * message out, command req/ ? initiator decremented by message in, status ack/ message out, command dack/ * * in dma burst mode, the transfer counter decrements on the leading edge of rd/, dbrd/, dbwr/, and dack/ as follows: 76543210 default 00000000
4-6 registers copyright 1995?002 by lsi logic corporation. all rights reserved. ? target decremented by data in phase ? dma write, multiplex bus mode dbwr/ ? dma write, nonmultiplex bus mode dack/ ? initiator decremented by synchronous data in ? dma read, multiplex bus mode dbrd/ ? dma read, nonmultiplex bus mode dack/ data out ? dma write, multiplex bus mode dbwr/ ? dma write, nonmultiplex bus mode dack/ note: dack/ can decrement the counter even if rd/ or wr/ do not go true. false dack/s can cause the counter to get out of sync with the data stream, leading to subtle errors that are dif?ult to trace. when false dack/s are expected to interfere with a temporarily suspended dma operation, the dreq high-z bit in con?uration 2 (con? 2) should be set while the dma is suspended. with two exceptions, non-dma commands do not use the counter. during bus-initiated selection and during the target receive command sequence, the fsc decodes the group code ?ld of the command descriptor block (cdb), loads the counter with the number of bytes in the cdb, then decrements once for every byte received.
standard register set 4-7 copyright 1995?002 by lsi logic corporation. all rights reserved. register: 0x02 fifo read/write register bank 0 or 1 this register is a 16-by-9-bit, first-in-first-out buffer between the scsi bus and memory. read chapter 2, ?unctional description, to understand its use during scsi transactions. the scsi bus may transfer 8- or 9-bit bytes to the fifo, depending on the parity control bit settings (refer to table 2.1 on page 2-7 for details). the microprocessor may transfer 8-bit bytes to or from the fifo using cs/ and rd/ or wr/, and the address bits. an external dma controller may transfer 8 or 9-bit bytes to the fifo using dack/ and rd/ or wr/. when accessed by cs/, the address bits must be valid. when accessed by dack/, the address bits are ignored. the bottom fifo element and the fifo ?gs are initialized to zero after hardware reset, chip reset command, or flush fifo command and at the beginning of bus-initiated selection or reselection. the contents of the rest of the fifo are not changed by any reset but when the ?gs are zero, successive fifo reads access the bottom register. this register changes during any dma or scsi bus activity. the default value of this register is 0x00. 76543210 default 00000000
4-8 registers copyright 1995?002 by lsi logic corporation. all rights reserved. register: 0x03 command read/write register bank 0 or 1 this register is a two-deep, 8-bit read/write register that gives commands to the fsc. up to two commands may be stacked in the command register. the second command may be written before the fsc completes (or even starts) the first. reset chip, reset scsi bus, set attention immediate, and target stop dma execute immediately (within four cycles of being loaded); all others wait for the previous command to complete. the last executed (or executing) command remains in the command register and may be read by the microprocessor. reading the command register has no effect on its contents. the internal sequencer maintains a working copy of the bottom of the command fifo. certain conditions cause the working copy to be cleared, allowing the next command to fall through into the sequencer. if an interrupt was pending prior to these conditions occurring, the command sequencer remains reset until the interrupt register is read. these conditions are as follows: ? hardware reset ? software reset ? scsi bus reset ? scsi bus disconnect ? bus-initiated selection or reselection ? select command ? reconnect command if atn/ is set ? select or reselect time-out ? target terminate command ? parity error detected in target mode ? assertion of atn/ in target mode 76 0 endma command code (cc) default 0 0000000
standard register set 4-9 copyright 1995?002 by lsi logic corporation. all rights reserved. ? any phase change in initiator mode (except when issuing a sequence command) ? illegal command notes: ? non-dma send commands should not be stacked. ? commands that transfer data in one direction should not be stacked with commands that transfer data in the opposite direction. ? after a hardware reset or reset chip command, a nop is required to ?l the command register. if two commands are placed in the command register, two interrupts may result. if the ?st interrupt is not serviced before the second ?ishes, the second interrupt is placed behind the ?st. the ?st interrupt must be serviced before issuing a third command. when the interrupt register is read by the host to service the ?st interrupt, the contents of the status register, sequence step register, and interrupt register change to describe the second interrupt. when using stacked commands, the features enable bit ( con?uration 2 (con? 2) , bit 6) should be set to latch the scsi phase bit in the status register at the completion of each stacked command. endma enable dma 7 when bit 7 is set, the command is a dma instruction. when it is not set, the command is a non-dma instruction. dma instructions load the internal byte counter with the value in the transfer count register, without changing the count register. if the transfer terminates prematurely, the bits in the status , sequence step , and interrupt registers indicate why. cc command code [6:0] the fsc commands are shown in table 5.1 . bits 6, 5, and 4 specify a mode group, as shown in the following illustration. commands from the miscellaneous group may be issued at any time. commands from the disconnected target or initiator groups are only accepted by the fsc if it is in the same mode as the command when it falls to the bottom of the command fifo. otherwise, an illegal command interrupt is generated. for example, after a hardware or software reset, the fsc is in the
4-10 registers copyright 1995?002 by lsi logic corporation. all rights reserved. disconnected state. a command from either the target group or the initiator group causes an illegal command interrupt. an enable selection/reselection command by itself does not change modes. however, if another scsi device then selects the fsc, it is in the target state; if another device reselects the fsc, it is then in the initiator state. similarly, any select command places the fsc in initiator mode, while the reselect sequence command places the fsc in target mode. register: 0x04 status read only register bank 0 or 1 this register contains important ?gs that indicate certain events have occurred. bits [7:3] are latched until the interrupt register is read, and are reset by a hard reset, but not by a scsi reset. the phase bits are not normally latched. they may be latched (for stacked commands) by setting con?uration 2 (con? 2) , bit 6. int interrupt 7 this bit is set whenever the fsc drives the int/ output true. it may be polled. it is buffered from the actual output so that in wired-or (shared interrupt) designs, this bit indicates whether the fsc is attempting to interrupt the microprocessor. hardware reset, the reset command, or a read from the interrupt register releases an active int/ signal and also clears this bit. bits 6 5 4 command mode 0 0 0 miscellaneous 0 0 1 initiator 0 1 0 target 1 0 0 disconnected state 76543210 int ge pe tc voc msg c/d i/o default 00000xxx
standard register set 4-11 copyright 1995?002 by lsi logic corporation. all rights reserved. ge gross error 6 this bit is set when one of the following occurs: ? the top of the fifo is overwritten ? the top of the command register has been overwritten ? direction of dma transfer is opposite to the direction of the scsi transfer ? an unexpected phase change in initiator role during synchronous data phase when the offset has not been reconciled these conditions do not cause an interrupt; a gross error may be detected only while servicing another interrupt. this bit is cleared by reading the interrupt register if the interrupt output is asserted. it is also cleared by a hardware reset or the reset command, but not scsi reset. pe parity error 5 this bit is set if parity checking is enabled in the con?uration 1 (con? 1) register and the fsc detects a scsi parity error on command, data, status or message bytes. detected parity errors do not cause an interrupt; they are merely reported with other interrupt-causing events. if a parity error is detected during an initiator information in phase, atn/ is automatically asserted on the scsi bus. this bit is cleared by reading the interrupt register if the interrupt output is asserted. hardware reset or the reset chip command clears this bit, but not scsi reset. tc terminal count 4 this bit is set when the transfer counter decrements to zero. it is not set by loading a zero into the transfer counter register, but resets when the transfer count is loaded. because a dma nop (0x80) command loads the transfer counter , it also clears this bit. a non-dma nop (00) does not load the counter and does not clear this bit. reading the interrupt register does not clear this bit. hardware reset or the reset chip command clears it, but scsi reset does not.
4-12 registers copyright 1995?002 by lsi logic corporation. all rights reserved. voc valid group code 3 when the fsc is selected, this bit decodes the group code field in the first byte of the command descriptor block (cdb). if the group code matches one defined in ansi x3.131-1986, this bit is set. an undefined group code (designated reserved by the ansi committee) leaves it not set. if the scsi-2 bit is set in the configuration 2 (config 2) register, group 2 commands are recognized as ten-byte commands and this bit is set. if the scsi-2 bit is cleared, group 2 commands are treated as reserved commands. groups 3 and 4 are always treated as reserved commands. a reserved group command causes the fsc to request six command bytes and does not set this bit. group 5 commands are recognized as twelve-byte commands and this bit is set. the fsc recognizes group 6 as six-byte vendor unique commands and group 7 as ten-byte vendor unique commands. the valid group code bit is cleared by reading the interrupt register if the interrupt output is asserted. it is also cleared by a hardware reset or the reset chip command, but not by a scsi reset. msg, c/d, i/o phase bits [2:0] these bits indicate the phase on the scsi bus. they may be latched or unlatched, depending on con?uration 2 (con? 2) , bit 6. when not latched, they indicate the phase at the time the status register was read. in keeping with the ansi de?ition of the phase signals, these bits must be stable during any status register read that follows an interrupt generated by the fsc. the phase bits may be latched to permit stacking fsc commands. when the latch is enabled, the scsi phase is latched upon command completion. these values are
standard register set 4-13 copyright 1995?002 by lsi logic corporation. all rights reserved. latched only if the features enable bit (bit 6) is set in the con?uration 2 (con? 2) register. the transparent latch is reopened when the interrupt register is read. register: 0x04 destination bus id write only register bank 0 or 1 the least signi?ant three bits of this register specify the encoded destination bus id for a selection or reselection command. these bits are binary encoded, with 000 0111 representing device id 7, which appears as 0x80 on the scsi bus. the most signi?ant ?e bits are reserved. the destination id is not changed by any reset; the states of these bits are unpredictable after power-up. bits 2 1 0 scsi bus phase 0 0 0 data out 0 0 1 data in 0 1 0 command 0 1 1 status 1 0 0 reserved 1 0 1 reserved 1 1 0 message out 1 1 1 message in 7 3210 r id2 id1 id0 default xxxxxxxx
4-14 registers copyright 1995?002 by lsi logic corporation. all rights reserved. register: 0x05 interrupt read only register bank 0 or 1 this 8-bit register is used in conjunction with the status register and sequence step register to determine the cause of an interrupt. reading this register when the interrupt output is true clears all three registers. the entire interrupt register is cleared (0x00) by a hardware reset or the reset command, but not scsi reset. the default value of this register is 0x00. note: this register should only be read when an interrupt is pending. the sequence step and status registers should be read prior to reading this register. srst scsi reset detected 7 this bit is set if scsi reset reporting is enabled in the con?uration 1 (con? 1) register and the chip detects a reset on the scsi bus. ilcmd illegal command 6 this bit is set when a reserved code is placed in the command register or when the command is from a mode group different than the mode the fsc is currently in. refer to the command register de?ition. an interrupt is generated when this bit is set. dis disconnect 5 in initiator mode, this bit is set when the target disconnects or a selection or reselection time-out occurs. when the fsc is in target mode, this bit is set if a terminate sequence or command complete sequence command causes the fsc to disconnect from the bus. 76543210 srst ilcmd dis bs fc resel si default 00000000
standard register set 4-15 copyright 1995?002 by lsi logic corporation. all rights reserved. bs bus service 4 this bit indicates that another device is requesting service. in target mode, it is set whenever the initiator asserts atn/ (attention). in initiator mode, it is set whenever the target is requesting an information transfer phase. fc function complete 3 this bit is set after any target mode command has completed. in initiator mode, it is set after a target has been selected (before transferring any command phase bytes), after command complete ?ishes, or after a transfer information command when the target is requesting message in phase. resel reselected 2 this bit is set during reselection phase to indicate that the fsc has been reselected as an initiator. si selection interrupt [1:0] these two bits distinguish and report three different types of selections as follows: bit 1 bit 0 indication 00 no selection interrupt 01 selected without atn/; fsc has been selected as a target with atn/ false 10 selected with atn/; fsc has been selected as a target with atn/ true 11 scam selection. fsc has detected a scam selection
4-16 registers copyright 1995?002 by lsi logic corporation. all rights reserved. register: 0x05 time-out write only register bank 0 or 1 under normal operation [when the enable delayed response to selection (endr) bit, bit 4 of the scsi control (scontrol) register, is cleared], this 8-bit, write only register speci?s the amount of time the fsc waits for a response during selection or reselection. (the fsc has no way to time-out if it never wins arbitration; it keeps trying inde?itely until it wins.) the time-out register is normally loaded to specify a time-out period of 250 ms to comply with the ansi standard. when endr is set, the fsc delays its response to selection based on the value of this register. in either case, the register value (rv) may be calculated from: for example, at 40 mhz, the register value that gives a 250 ms time-out period is 153 decimal or 0x99. the clock conversion factor is de?ed in the description of write address 0x09. to compute the register value using this formula when the clock conversion factor is zero, use eight, the number of clocks, rather than zero. the time-out register remains unchanged by any reset, and the states of these bits are unpredictable after power-up. 76543210 default xxxxxxxx rv (time-out period) (clk frequency) 8192 clock conversion factor () ------------------------------------------------------------------------------------------ - =
standard register set 4-17 copyright 1995?002 by lsi logic corporation. all rights reserved. register: 0x06 sequence step read only register bank 0 or 1 the lower three bits of this register indicate how far the internal sequencer was able to proceed in executing a sequenced command. this counter is incremented at certain points in sequenced commands to aid in error recovery if the command does not complete normally. this register is cleared by a hard reset, scsi reset, and by reading the interrupt register when an interrupt is pending. r reserved [7:4] som synchronous offset max 3 this bit is zero for asynchronous data transfers. for synchronous transfers, this bit is set. when this bit is clear, the synchronous offset counter has reached its maximum value. ss[2:0] sequence step [2:0] the sequence step counter is set to zero at the beginning of certain commands. the counter is then incremented at speci? points in the various algorithms to aid in error recovery. the possible states are described in chapter 5, ?ommand set. 7 432 0 r som ss[2:0] default 1 1 0 00000
4-18 registers copyright 1995?002 by lsi logic corporation. all rights reserved. register: 0x06 synchronous transfer period write only register bank 0 or 1 bits [4:0] of this register specify the minimum time between leading edges of successive req/ (request) or ack/ (acknowledge) pulses. synchronous data is transmitted or received at the rate of one byte every ? clocks (clk). the variable ? is related to the register value and the data transfer rate as shown in table 4.3 and table 4.4 . 7 543210 r clocks per byte default 0 0 000101
standard register set 4-19 copyright 1995?002 by lsi logic corporation. all rights reserved. table 4.3 transfer rate with 40 mhz clock (fastclk bit set) fast scsi bit value register value clocks per byte transfer rate (mbytes/s) 1 0x4 4 10.0 1 0x5 5 8.0 1 0x6 6 6.6 1 0x7 7 5.7 x 0x8 8 5.0 0 0x9 9 4.4 0 0xa 10 4.0 0 0xb 11 3.6 0 0xc 12 3.3 0 0xd 13 3.0 0 0xe 14 2.8 0 0xf 15 2.6 0 0x10 16 2.5 0 0x11 17 2.3 0 0x12 18 2.2 0 0x13 19 2.1 0 0x14 20 2.0
4-20 registers copyright 1995?002 by lsi logic corporation. all rights reserved. the upper three bits are reserved by lsi logic. this register defaults to 0x55 after hardware reset or the reset chip command (but not scsi reset). refer to the descriptions for the fastclk and fastscsi bits, con?uration 3 (con? 3) , bits 3 and 4, for information on fast scsi operation. note: any combination not listed in the above tables violates ansi standards, and should not be used. table 4.4 transfer rate with 25 mhz clock (fastclk bit clear) fast scsi bit value register value clocks per byte transfer rate (mbytes/s) 0 0x5 5 5.0 0 0x6 6 4.2 0 0x7 7 3.6 0 0x8 8 3.1 0 0x9 9 2.8 0 0xa 10 2.5 0 0xb 11 2.3 0 0xc 12 2.1 0 0xd 13 1.9
standard register set 4-21 copyright 1995?002 by lsi logic corporation. all rights reserved. register: 0x07 fifo flags read only register bank 0 or 1 the least signi?ant ?e bits of this register indicate how many bytes are currently in the fifo. the value is binary encoded. the ?gs should not be polled while transferring data because they are not stable while the scsi interface is changing the contents of the fifo. the upper three bits are duplicates of the sequence step register bits in normal mode. if test mode is enabled, bit 5 is set to indicate that the offset counter is not zero. not zero means that synchronous data may continue to be transferred. zero means that the synchronous offset count has expired, and the fsc does not transfer any more data until it receives an acknowledge. register: 0x07 synchronous offset write only register bank 0 or 1 bits [7:6] of this register control when the req/ and ack/ signals deassert by selecting one of four input clock edges. these bits only affect a synchronous data in or synchronous data out phase. the control over deassertion of these signals is measured in input clock cycles and is dependent on the status of the fastclk bit, con?uration 3 (con? 3) , bit 3, as shown in table 4.5 . 76543210 ss2 ss1 ss0 ff4 ff3 ff2 ff1 ff0 default 00000000 76543210 deassertion delay assertion delay synchronous/asynchronous 00000000
4-22 registers copyright 1995?002 by lsi logic corporation. all rights reserved. bits 5 and 4 control when req/ or ack/ asserts by selecting one of four input clock edges. assertion of the req/ and ack/ signals is not dependent on the fastclk bit. the assertion delay is shown in table 4.6 . the least signi?ant four bits of this register specify whether the fsc transfers data phase bytes synchronously or asynchronously. zero speci?s asynchronous transfer. any other value speci?s the synchronous offset, the number of data phase bytes that may be sent synchronously without an acknowledge (either req/ or ack/), depending on whether the fsc is in initiator or target mode. table 4.5 req/ ack/ deassertion delay selection fastclk status synchronous offset register bits [7:6] req/ ack/ deassertion delay (input clock cycles) 1 00 no delay (default) 1 01 1/2 clock 1 10 1 clock 1 11 1 1/2 clocks 0 00 no delay 0 01 1/2 clock early 0 10 1 clock 0 11 1/2 clock table 4.6 req/ ack/ assertion delay selection synchronous offset register bits [5:4] req/ ack/ assertion delay (in input clock cycles) 00 0 (default) 01 1/2 clock 10 1 clock 11 1 1/2 clocks
standard register set 4-23 copyright 1995?002 by lsi logic corporation. all rights reserved. when transmitting to the scsi bus, the fsc stops sending bytes when it reaches this offset, and thereafter sends one byte for every acknowledge it receives from the other scsi device(s). when receiving from the scsi bus, the fsc sends an acknowledge every time a byte is removed from its fifo on the dma interface. the maximum offset of 15 allows a receiving fsc to store data in its fifo while the external dma controller gains control of the memory bus. the maximum offset is 15 for nonburst mode operation, and 7 for burst mode. the synchronous offset is cleared (00) by hardware reset or a software chip reset, but not scsi reset. figure 4.1 illustrates the req/ ack/ deassertion delay. figure 4.1 req/ ack/ deassertion delay 01 2 3 01 2 3 (bits [5:4]) (bits [7:6]) fastclk enabled 01 2 3 01 2 3 (bits [5:4]) (bits [7:6]) fastclk disabled clk req/ ack/ sync offset register value clk req/ ack/ sync offset register value note: the input clock duty cycle affects the half clock assertion/deassertion delays.
4-24 registers copyright 1995?002 by lsi logic corporation. all rights reserved. register: 0x08 con?uration 1 (con? 1) read/write register bank 0 this 8-bit read/write register speci?s various operating conditions for the fsc. any bit pattern written to this register may be read back and should be identical. the default value of this register is 0x00. slow slow cable mode 7 slow cable mode is needed when cabling conditions cause scsi bus violations. it compensates for excessive capacitive loading on the scsi data signals by inserting an extra clk period between data being asserted on the bus and req/ or ack/ being driven true. this bit is cleared (0) by hardware reset or the reset command, but not scsi reset. srd scsi reset reporting interrupt disable 6 this bit disables the reporting of a scsi reset. if the scsi reset signal goes true when this bit is set, the fsc disconnects from the scsi bus and remains idle in the disconnected state without interrupting the host. if the bit is not set, the fsc responds to the scsi reset by ?st interrupting the host. this bit is cleared by hardware reset or the chip reset command, but not scsi reset. ptest parity test mode 5 with this bit set, the parity bit equals bit 7 when unloading the fifo to the scsi bus and using a dma command. for non-dma commands, standard odd parity is generated on the scsi bus. this allows parity errors to be created so that hardware and software may be tested. this bit must not be set during normal operation. refer to section 2.3, ?arity checking and generation, on page 2-6 . this bit is cleared by hardware reset or the chip reset command, but not scsi reset. 765432 0 slow srd ptest pchk ctest mbid default 00000000
standard register set 4-25 copyright 1995?002 by lsi logic corporation. all rights reserved. pchk enable parity checking 4 when this bit is set, the fsc checks parity on scsi bytes during any information transfer phase except when receiving pad bytes. detected parity errors causes the parity error bit to be set in the status register but does not cause an interrupt. in initiator role, bad parity on incoming scsi bytes also sets atn/ (attention) on the scsi bus. when this bit is not set, parity is not checked, the bit in the status register is not set, and atn/ is not asserted. refer to section 2.3, ?arity checking and generation, on page 2-6. this bit is cleared by hardware reset or the reset command, but not by a scsi reset. ctest chip test mode enable 3 when this bit is set, the chip is placed in a special test mode which enables the test register at address 0x0a. after it has been set, the chip must be reset (hard or soft but not scsi) before normal operation can begin. this bit should not be set during normal operation. this bit is cleared by hardware reset or the reset command, but not scsi reset. mbid my bus id [ 2:0] this bit ?ld is the bus id of this device. it is the id to which the fsc responds during bus-initiated selection or reselection, and the id that the fsc uses to arbitrate for the bus. this three-bit ?ld is binary encoded. it is reset by hard reset but not by scsi reset; after power-up the states of these bits are unpredictable.
4-26 registers copyright 1995?002 by lsi logic corporation. all rights reserved. register: 0x09 clock conversion write only register bank 0 this register must be set according to the clk (clock) input frequency. all timings longer than 400 ns depend on this register correctly agreeing with the clk frequency. the clock conversion factor is equal to the binary encoded version of the least signi?ant three bits. it should be set to one of the seven values shown in table 4.7 . note: a clock conversion factor of 0b000 indicates eight clocks. these bits must never be loaded with a binary 0b001. hardware reset or the reset command sets the clock conversion factor to a binary 0b010. the upper ?e bits of this register are reserved. 7320 r clock conversion bits default x x x x x010 table 4.7 clk frequency vs. clock conversion factor clk frequency (mhz) clock conversion factor 10 0b010 10.01 to 15 0b011 15.01 to 20 0b100 20.01 to 25 0b101 25.01 to 30 0b110 30.01 to 35 0b111 35.01 to 40 0b000
standard register set 4-27 copyright 1995?002 by lsi logic corporation. all rights reserved. register: 0x0a test write only register bank 0 this register is enabled by setting the special test mode bit in con?uration 1 (con? 1) register at address 0x08. after test mode has been entered, a hardware reset or the reset command must occur before normal operation can begin. these bits must not be set during normal chip operation. r reserved [7:5] r reserved [4:3] these bits must be set to 0. high-z all outputs to high impedance 2 when this bit is set, all bidirectional and all output pins go to high impedance and do not signi?antly load a ttl or compatible device. init initiator mode 1 when this bit is set, the fsc is artificially forced into initiator mode. any initiator command is accepted by the fsc. for example, a set atn command causes atn/ to be driven on the scsi bus even if the fsc is disconnected. tar target mode 0 when this bit is set, the fsc is artificially forced into target mode. any target command is accepted by the fsc. for example, a dma command loads or unloads the fifo and sets the scsi phase, data, and req/ signals even if arbitration and selection have not occurred. 73210 r high-z init tar default 0 0 0 0 0000
4-28 registers copyright 1995?002 by lsi logic corporation. all rights reserved. register: 0x0b con?uration 2 (con? 2) read/write register bank 0 after hardware reset or the reset command, the bits in this register are all cleared, which makes the chip compatible with lsi53c90 family software. any bit pattern written to this register may be read back and should be identical. the default value of this register is 0x20. r reserved 7 this bit must be set to 0. fe features enable 6 this bit is cleared by hardware reset or the software reset command, and is not affected by scsi reset. when set, this bit enables all of the following features: ? the scsi phase is latched at each command completion. this permits simpler software routines for stacked commands. when this bit is not set, the phase bits reported in the status register are live indicators of the state of the scsi phase lines. ? the transfer counter high/id (0x0e) register is enabled, which extends the transfer counter from 16 to 24 bits. if other conditions are met, setting this bit also allows the chip revision code to be read (see the transfer counter high/id register description for more information on this feature). r reserved 5 this bit must be set to 0. dhz dreq high impedance 4 when this bit is set, the dreq output (dma request) goes to high impedance and does not signi?antly load a ttl-compatible device. this is useful when several 76543210 rfe r dhz scsi2 bpa r dpe default 00 0000 00
standard register set 4-29 copyright 1995?002 by lsi logic corporation. all rights reserved. devices share the dma request line (known as wired-or). when this bit is set, the fsc ignores any activity on the dack/ (dma acknowledge) input. when this bit is cleared, the dreq output is driven to ttl high or low voltages. when this bit is cleared, dack/ is able to decrement the transfer counter and load or unload the fifo, depending on wr/ or rd/. dack/ should not pulse true without rd/ or wr/ because the transfer counter may decrement without transferring any data. refer to the transfer counter register description. scsi2 scsi-2 3 setting this bit allows the fsc to support two new features adopted in scsi-2: the 3-byte message exchange for tagged-queuing and group 2 commands. similar features also can be set independently in the con?uration 3 (con? 3) register. tagged-queuing when this bit is set and the fsc is selected with atn/ (attention), it requests either one or three message bytes depending on whether atn/ remains true or goes false. if atn/ is still true after the first byte has been received, the fsc may request two more message bytes before switching to command phase. if atn/ goes false, it switches to command phase after the first message byte. when the bit is not set, it requests a single message byte (as a target) when selected with atn/, and aborts the selection sequence (as an initiator) if the target does not switch to command phase after one message byte has been transferred. refer to section 2.2, ?us-initiated sequences, on page 2-3 for details. group 2 commands when the scsi-2 bit is set, group 2 commands are recognized as 10-byte commands. receiving a group 2 command with this bit set sets the valid group code bit in the status register. if the scsi-2 bit is not set, the fsc treats group 2 commands as reserved commands, it requests only six bytes in command phase, and does not set the valid group code status bit.
4-30 registers copyright 1995?002 by lsi logic corporation. all rights reserved. bpa target bad parity abort 2 when this bit is set, the fsc aborts a receive command or receive data sequence command when the fsc detects a parity error. r reserved 1 this bit should be set to 0. if this bit is set to 1, then incorrect parity may result when moving data from the fifo to the scsi bus. dpe dma parity enable 0 when this bit is set, parity from the host dbp pins is loaded into the fifo when dack/ and wr/ are both true. when this bit is not set, the fsc generates parity from the host data bus when dack/ and wr/ are both true and places it in the fifo along with the data from which it was generated. when the fsc is moving data from the fifo to the scsi bus, it ?gs outgoing parity errors only if this bit is set. register: 0x0c con?uration 3 (con? 3) read/write register bank 0 after a hardware reset or a software chip reset, the bits in this register are all cleared, which makes the chip compatible with lsi53c90 family software. any bit pattern written to this register may be read back and should be identical, except that bit 2 remains low. imrc id message reserved check 7 this bit allows a second level of checking for the validity of an id message. the most signi?ant bit of an id message byte is always checked, and must be one, or the chip interrupts. when this bit is set, bits [5:3] of the id message are also checked and must be zero, or the 76543210 imrc qte cdb10 fscsi fclk r adma t8 default 00000 000
standard register set 4-31 copyright 1995?002 by lsi logic corporation. all rights reserved. chip interrupts. this check occurs if the chip is selected with atn/ true. if the validation check fails, the selection sequence halts and the chip generates an interrupt. qte queue tag enable 6 when this bit is set, the lsi53CF92A can receive 3-byte messages during bus-initiated select with atn. a similar feature is also enabled by setting bit 3 in the con?uration 2 (con? 2) register. the message bytes consist of a one-byte identify message and a two-byte queue tag message. the middle byte is the tagged queue message itself and the last byte is the tag value (0 to 255). when this bit or the scsi-2 bit is set, the second byte is checked to see if it is a valid queue tagging message. if the value of the byte is not 0x20, 0x21, or 0x22, the sequence halts and an interrupt is generated. when this bit is not set, the chip aborts the select with atn sequence after it receives one identify message byte, if atn/ is still asserted. cdb10 cdb10 5 when this bit is set, 10-byte group 2 commands are recognized as valid command descriptor blocks (cdb). the target command sequence receives ten group 2 command bytes and sets the valid group code bit ( status register, bit 3). when this bit and the scsi-2 bit are not set, the target command sequence receives only six group 2 command bytes and does not set the valid group code bit. the group code de?es how many bytes are in the cdb, and determines how many bytes to request while driving command phase. this feature is also enabled or disabled by setting or clearing bit 3 in the con?uration 2 (con? 2) register. fscsi fastscsi 4 bits 4 and 3 of this register inform the device that it is connected to a fast clock, and to select between fast scsi timings and scsi-1 timings. see table 4.8 for transfer rates based on these bits. also, the scsi req/ and ack/ input ?tering period is determined by the state of this bit. when this bit is set, the ?tering period is 30 ns. when it is reset, the period is 60 ns. see figure 6.2 on page 6-5 for details.
4-32 registers copyright 1995?002 by lsi logic corporation. all rights reserved. fclk fastclk 3 along with bit 4, this bit informs the device that it is connected to a fast clock, and to select between fast scsi timings and scsi-1 timings. fast scsi operation requires a 40 mhz clock. a fast clock is one with a frequency greater than 25 mhz. the fastclk bit also controls the deassertion delay of the req/ and ack/ signals. see register 0x07 synchronous offset, page 4-21 . bits 4 and 3 of this register affect the scsi transfer rate as shown in table 4.8 . r reserved 2 this bit must be set to 0 . adma alternate dma mode 1 this bit may be set only when the threshold eight bit (bit 0) in this register is set. all possible combinations for using bits 1 and 0 of this register are shown in table 4.9 : setting this bit modi?s the dma interface to take advantage of the demand mode using a dma controller when the threshold eight bit is also set. refer to the description for section 2.5.4, ?ma burst mode, on page 2-11 for details. when this bit is set, dma data is strobed into or out of the fsc during dma reads and writes as follows: table 4.8 synchronous transfer rate and minimum clocks/byte minimum clocks/byte sync transfer (mbytes/s) bit 4 bit 3 asynch synch x0 2 5 5 01 3 8 5 11 3 4 10 table 4.9 dma modes bit 1 bit 0 function 0 0 normal dma mode 0 1 threshold eight mode 1 0 reserved 1 1 dma burst mode
standard register set 4-33 copyright 1995?002 by lsi logic corporation. all rights reserved. ? dma write for multiple dma writes per dreq, dack/ remains asserted while dbwr/ toggles for each write. the functionality of dack/ and dreq are unchanged for single dma writes per dreq. ? dma read in the multiplexed bus con?uration mode, during multiple dma transfers, dack/ remains asserted while dbrd/ toggles for each transfer. the fsc outputs data when both dack/ and dbrd/ are true. in the nonmultiplexed bus con?uration mode, dack/ must toggle for each dma read. the fsc outputs data when dack/ is true. note: rd/ is not used in this mode. if the burst consists of one transfer, dreq obeys the nonburst timings. if the burst consists of two or more transfers, dreq obeys the burst mode timings. if the fsc is operating as an initiator and a phase change occurs before the ?st dreq has been acknowledged, dreq obeys the nonburst timings. otherwise, dreq obeys the burst mode timings. refer to figures 2.2 and 2.3 for burst mode timing relationships. if less than eight bytes remain as a burst begins at the end of a transfer, the fsc switches out of burst mode for the last one to seven bytes; these bytes are transferred in normal dma mode. tb threshold eight 0 setting this bit causes the fsc to delay assertion of dreq (dma request) until it can transfer eight bytes. this higher threshold applies only to scsi data phases. the threshold for all other scsi phases is one byte. this bit must be set if using alternate dma mode. when threshold eight is set, the maximum synchronous offset is limited to seven. dreq goes true during dma reads and writes as follows.
4-34 registers copyright 1995?002 by lsi logic corporation. all rights reserved. ? dma write to fifo dreq is true whenever the top eight bytes of the fifo are empty. ? dma read from fifo ? end of transfer target mode: dreq is set when the transfer counter is zero or atn/ is set. initiator synchronous data in: dreq is true when the transfer counter is less than eight. initiator mode, not synchronous data in: dreq is true when the transfer counter is zero, or after any phase change. ? not end of transfer initiator synchronous data in: dreq is true if the transfer counter is greater than seven and the bottom eight bytes of the fifo are full. not initiator synchronous data in: dreq is true whenever the bottom eight bytes of the fifo are full. register: 0x0d con?uration 4 (con? 4) read/write register bank 0 or 1 the reserved bits in this register are ignored on writes. this register is reset to zero on power-up or chip reset, but not on scsi reset. note: this register is accessible in either register bank 0 or 1. r reserved 7 this bit is set to 1 as soon as the chip is enabled. r reserved [6:4] these bits remain set to 0. 7 43210 r rbs ean r default 1 0 0 000 1 1
standard register set 4-35 copyright 1995?002 by lsi logic corporation. all rights reserved. rbs register bank select 3 when this bit is set, access to register bank 1 (scam registers) is enabled. when this bit is clear, access to register bank 0 (normal registers) is enabled. ean enable active negation 2 when enabled, the scsi data, parity, req/, and ack/ outputs actively drive to both high and low logic levels. refer to section 1.3, ?olerant technology, on page 1-2 for details. this bit should be set when transferring data at fast scsi rates. r reserved [1:0] these bits remain set to 1. register: 0x0e transfer counter high/id read/write register bank 0 this register extends the transfer counter to 24 bits. this register is only enabled when the features enable bit is set. refer to the descriptions for registers 0x00?x01 for additional information on the transfer counter. reading this register can also provide the chip revision code when the following conditions are met: ? a hard reset has occurred; and ? the register has not been loaded with a transfer count. 7320 cfid rl default 10010100
4-36 registers copyright 1995?002 by lsi logic corporation. all rights reserved. the following bit descriptions apply when the previous conditions are met. cfid chip family id [7:3] these bits identify the chip family, and are currently ?ed at 0b10010. rl chip revision level [2:0] these bits identify the current revision level of the chip, and are currently set to 0x96. register: 0x0f reserved register bank 0 4.2 scam register set to provide register structures for directly controlling and observing scsi bus activity thus providing scam functionality, an additional addressing mode was created for the lsi53CF92A to allow access to the new registers. this is because the original address map for the lsi53CF92A was limited to 16 registers and only two read only addresses were available. the address map is extended to 24 locations through a bank- select mechanism whereby two sets of registers are mapped to addresses 0x08?x0f. the control bit for selecting the scam register set is bit 3 in the con?uration 4 (con? 4) register, and is visible in either register bank. the complete register map including scam registers is shown in table 4.2 and in appendix a, ?egister map. 7 0 r x x x x x x x x
scam register set 4-37 copyright 1995?002 by lsi logic corporation. all rights reserved. register: 0x08 scsi control (scontrol) read/write register bank 1 this register controls fsc actions and response in low-level mode. this register is cleared by the reset chip command, assertion of the reset pin, scsi bus reset, or chip power-up. r reserved 7 totest time-out test 6 when this bit is set, the internal counter, which controls selection and delayed scam selection time-out delays, is loaded with a shorter time-out value (8 as opposed to the normal value of 480). this bit is for test purposes only and should not be used for normal chip operation. lpc low level parity control 5 during low-level scsi programming (low level true), parity is generated from the contents of the scsi output data latch (sodl) register. when this bit is set, the generated parity is even. when this bit is cleared, odd parity is generated. endr enable delayed response to selection 4 when this bit is set, the fsc delays its response to selection based on the value programmed in the select/reselect time-out register. the fsc, upon detecting that it is being selected, waits for the speci?d time, then asserts bsy/ and continues its normal response to selection. if the initiator drops bsy/ before the delay period expires, the fsc ignores the selection attempt. this functionality allows a scam master to scan the scsi bus for scam tolerant (?ld? devices using short selection time-outs. unassigned scam slaves do 7 6 54321 0 r totest lpc endr enss adb arb ll default 0 0 00000 0
4-38 registers copyright 1995?002 by lsi logic corporation. all rights reserved. not respond to this initial bus scan because of their delayed response. after a scam slave has been assigned an id, this bit should be cleared to enable normal selection response. enss enable scam selection response 3 when this bit is set, the fsc monitors the scsi bus for scam selections. when the fsc detects a valid scam selection, it asserts sel/ and msg/, sets both the sel and satn bits in the interrupt register, and asserts the interrupt pin. adb assert data bus 2 when set, this bit allows the contents of the scsi output data latch (sodl) register to be enabled as chip outputs. parity is also generated and asserted onto the scsi data bus. the low level parity control bit determines whether the generated parity is even or odd. arb arbitrate 1 when set, this bit starts the arbitration process when a bus-free condition has been detected. prior to setting this bit, the scsi output data latch (sodl) register should contain the proper scsi id value. one scsi id bit should be set for normal low-level arbitration; no id bits should be set for scam arbitration without an id. the chip waits for a bus-free condition before entering the arbitration phase. the status of the arbitration phase may be determined by reading the scsi status register, bits [1:0]. ll low level 0 setting this bit places the fsc into low-level mode. in this mode, direct control of the scsi bus is possible. scsi bus arbitration, selection, and data transfers are performed by manually asserting and monitoring scs bus signals. when this bit is cleared, both the scsi output control latch (socl) and scsi output data latch (sodl) registers are held reset. the current bus status using the scsi bus control lines (sbcl) and scsi bus data lines (sbdl) registers is available regardless of the state of this bit.
scam register set 4-39 copyright 1995?002 by lsi logic corporation. all rights reserved. register: 0x09 scsi status (sstatus) read only register bank 1 this register provides scsi status information for use during low-level mode. r reserved [7:4] sdp scsi parity status 3 this bit indicates the state of the scsi data parity signal (bit set = scsi parity asserted). this bit is not latched; it provides a true representation of what is on the scsi bus at the time this register is read. srst scsi reset status 2 this bit indicates the state of the scsi reset signal (bit set = scsi reset asserted). this bit is sampled; it provides a representation of what was on the scsi bus one synchronization delay prior to the time this register is read. arb4 arbitration delay4 1 this bit is set when four arbitration delays have passed since the fsc detected bus-free and started arbitrating for the scsi bus. arb1 arbitration delay1 0 this bit is set when one arbitration delay has passed since the fsc detected bus-free and started arbitrating for the scsi bus. 7 43210 r sdp srst arb4 arb1 default 0 0 0 0xx00
4-40 registers copyright 1995?002 by lsi logic corporation. all rights reserved. register: 0x0a scsi output control latch (socl) read/write register bank 1 this register provides low-level control of the scsi bus control signals. this register is cleared by the reset chip command, assertion of the reset pin, a scsi bus reset, chip power-up, and held reset whenever the low level mode bit is cleared. req (bit set = assert scsi req/) 7 ack (bit set = assert scsi ack/) 6 bsy (bit set = assert scsi bsy/) 5 sel (bit set = assert scsi sel/) 4 atn (bit set = assert scsi atn/) 3 msg (bit set = assert scsi msg/) 2 c/d (bit set = assert scsi c/d/) 1 i/o (bit set = assert scsi i/o/) 0 76543210 req ack bsy sel atn msg c/d i/o default 00000000
scam register set 4-41 copyright 1995?002 by lsi logic corporation. all rights reserved. register: 0x0b scsi bus control lines (sbcl) read only register bank 1 this read only register provides status of the scsi bus control signals. these bits are sampled; they are a representation of what was on the scsi bus one synchronization delay prior to the time this register is read. req (bit set = scsi req/ asserted) 7 ack (bit set = scsi ack/ asserted) 6 bsy (bit set = scsi bsy/ asserted) 5 sel (bit set = scsi sel/ asserted) 4 atn (bit set = scsi atn/ asserted) 3 msg (bit set = scsi msg/ asserted) 2 c/d (bit set = scsi c/d/ asserted) 1 i/o (bit set = scsi i/o/ asserted) 0 76543210 req ack bsy sel atn msg c/d i/o default 00000000
4-42 registers copyright 1995?002 by lsi logic corporation. all rights reserved. register: 0x0e scsi output data latch (sodl) read/write register bank 1 sd[7:0] (bit set = assert scsi data bit) [7:0] this register provides low-level control of the scsi bus data signals. this register is cleared by the reset chip command, assertion of the reset pin, a scsi bus reset, chip power-up, and held reset whenever the low level mode bit is cleared. the contents of this register are placed onto the scsi bus during low-level arbitration (arb bit set) or by setting the assert data bus bit in the scsi control (scontrol) register. register: 0x0f scsi bus data lines (sbdl) read only register bank 1 sd[7:0] (scsi data bits, active high) [7:0] this read only register provides status of the scsi bus data signals. these bits are not latched; they are a true representation of what is on the scsi bus at the time this register is read. 7 0 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 default 00000000 7 0 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 default xxxxxxxx
lsi53CF92A fast scsi controller 5-1 copyright 1995?002 by lsi logic corporation. all rights reserved. chapter 5 command set all lsi53CF92A instructions may be issued in two forms: dma and non-dma. dma commands move data between memory and the scsi bus, while non-dma commands move data between the fifo and the scsi bus. non-dma commands require the microprocessor to move data between the fifo and memory. dma commands require an external dma controller to move data between the fifo and memory. a command that is issued to the command register with bit 7 of the command register set is a dma command. a command that is issued with bit 7 not set is a non-dma command. dma commands load the transfer counter with the value in the transfer counter register, so the transfer counter register must be loaded before any dma command is issued. the word ?equence in the command name indicates that the sequence step register is affected by executing the command. check the sequence step register after using these commands to verify the command completed normally or to aid in data recovery if the command did not complete normally. this chapter contains the following sections: ? section 5.1, ?llegal commands ? section 5.2, ?iscellaneous command group ? section 5.3, ?isconnected state command group ? section 5.4, ?nitiator command group ? section 5.5, ?arget command group table 5.1 lists the command set.
5-2 command set copyright 1995?002 by lsi logic corporation. all rights reserved. table 5.1 command set non-dma dma 1 command register [7:0] command interrupt 7 6 5 4 3 2 1 0 miscellaneous group 0x00 0x80 x 0 0 0 0 0 0 0 nop no 0x01 0 0 0 0 0 0 0 1 flush fifo no 0x02 0 0 0 0 0 0 1 0 reset chip no 0x03 0 0 0 0 0 0 1 1 reset scsi bus yes 2 0x45 0 1 0 0 0 1 0 1 disable selection/reselection yes 7 6 5 4 3 2 1 0 disconnected state group 0x40 0xc0 x 1 0 0 0 0 0 0 reselect sequence yes 0x41 0xc1 x 1 0 0 0 0 0 1 select without atn sequence yes 0x42 0xc2 x 1 0 0 0 0 1 0 select with atn sequence yes 0x43 0xc3 x 1 0 0 0 0 1 1 select with atn and stop sequence yes 0x44 0xc4 x 1 0 0 0 1 0 0 enable selection/reselection no 0x46 0xc6 x 1 0 0 0 1 1 0 select with atn3 sequence yes 0x47 0xc7 x 1 0 0 0 1 1 1 reselect3 sequence yes 7 6 5 4 3 2 1 0 initiator group 0x10 0x90 x 0 0 1 0 0 0 0 transfer information yes 0x11 0x91 x 0 0 1 0 0 0 1 initiator command complete sequence yes 0x12 0 0 0 1 0 0 1 0 message accepted yes 0x18 0x98 x 0 0 1 1 0 0 0 transfer pad yes 0x1a 0 0 0 1 1 0 1 0 set atn no 0x1b 0 0 0 1 1 0 1 1 reset atn no 0x1e 0 0 0 1 1 1 1 0 set atn immediate no 76543210 targetgroup 0x20 0xa0 x 0 1 0 0 0 0 0 send message yes 0x21 0xa1 x 0 1 0 0 0 0 1 send status yes 0x22 0xa2 x 0 1 0 0 0 1 0 send data yes 0x23 0xa3 x 0 1 0 0 0 1 1 disconnect sequence yes 0x24 0xa4 x 0 1 0 0 1 0 0 terminate sequence yes 0x25 0xa5 x 0 1 0 0 1 0 1 target command complete sequence yes
illegal commands 5-3 copyright 1995?002 by lsi logic corporation. all rights reserved. 5.1 illegal commands writing an illegal command to the command register causes an illegal command interrupt to be generated. an illegal command is any command outside of the speci?d mode commands or any unsupported command. an illegal command interrupt must be cleared prior to writing another command to the command register. 5.1.1 stacked commands the command register is a two-deep, eight-bit read/write register that gives commands to the fsc. if dma commands are to be stacked, the transfer count must be loaded prior to loading the respective command. command stacking should only be used during data in and data out phase. if stacking is used in initiator mode, it is recommended that the features enable bit in con?uration 2 (con? 2) be set. this causes the scsi phase lines to be latched at the end of a command. 76543210 targetgroup 0x27 0 0 1 0 0 1 1 1 disconnect no 0x28 0xa8 x 0 1 0 1 0 0 0 receive message yes 0x29 0xa9 x 0 1 0 1 0 0 1 receive command yes 0x2a 0xaa x 0 1 0 1 0 1 0 receive data yes 0x2b 0xab x 0 1 0 1 0 1 1 receive command sequence yes 0x04 0 0 0 0 0 1 0 0 target abort dma no 3 1. a dash (? in the dma column means that the transfer counter is loaded but no dma operation occurs. 2. the command causes an interrupt if the scsi reset reporting is not disabled in con?uration 1 (con? 1) register. 3. the command itself does not cause an interrupt. however, it may allow a stalled command to ?ish and generate an interrupt. table 5.1 command set (cont.) non-dma dma 1 command register [7:0] command interrupt
5-4 command set copyright 1995?002 by lsi logic corporation. all rights reserved. 5.2 miscellaneous command group miscellaneous commands can be executed and are valid in any mode. table 5.2 lists the miscellaneous commands. 5.2.1 no-operation (nop) the fsc requires this command only after hardware reset or the reset chip command to free the command register. a dma nop (0x80) may load the transfer counter with the value in the transfer counter register. no interrupt is generated from this command. 5.2.2 flush fifo this command initializes the fifo to the empty condition by resetting the fifo ?gs and setting the bottom byte of the fifo to zero. 5.2.3 reset chip this command resets all functions in the chip and returns it to a disconnected state. the command has the same effect as a hardware reset. table 5.2 miscellaneous commands non-dma dma mnemonic 0x00 0x80 no operation (nop) 0x01 flush fifo 0x02 reset chip 0x03 reset scsi bus 0x45 disable selection/reselection
miscellaneous command group 5-5 copyright 1995?002 by lsi logic corporation. all rights reserved. 5.2.4 reset scsi bus this command asserts the rst/ (scsi reset output) signal for t2 s, where: t2 = 130 (clk period) (ccf) ccf = clock conversion factor. refer to the description of write register 0x09 in chapter 4, ?egisters. for ccf = 0, indicating 8 clocks, substitute 8 for 0 in this calculation. clk is the clock input to the fsc. an interrupt is generated unless it is disabled in the config 1 register. 5.2.5 disable selection/reselection this command disables an earlier enable selection/reselection command. if bus-initiated selection or reselection has not begun when this command is received by the fsc, it generates a function complete interrupt. if bus-initiated selection or reselection has begun, this command (and all other commands) is ignored. refer to section 2.2.1, ?us-initiated selection, on page 2-4, and section 2.2.2, ?us-initiated reselection, on page 2-5, for details. when this command is loaded into the command register, any bus-initiated selection or reselection that is already requested begins immediately. because there is no delay in execution of the selection or reselection, the function complete interrupt bit is not set inadvertently if the selection or reselection sequence continues after this command has been loaded.
5-6 command set copyright 1995?002 by lsi logic corporation. all rights reserved. 5.3 disconnected state command group if any of the disconnected state commands are received by the fsc when it is not in the disconnected state, the command is ignored, the command register is cleared, and the fsc generates an illegal command interrupt. table 5.3 lists the disconnected state commands. 5.3.1 reselect sequence this command causes the fsc target to arbitrate for the bus and then enter the reselection phase when it wins arbitration. the identify message, required by scsi protocol, must either be placed in the fifo by the microprocessor before issuing the command; or must be transferred by dma, which involves setting the transfer count to one and setting up the external dma controller. in either case, the time-out and destination bus id registers must have been programmed previously. the sequence terminates early if a reselect time-out occurs. if it terminates normally, a function complete interrupt occurs. table 5.3 disconnected state commands non-dma dma mnemonic 0x40 0dxc0 reselect sequence 0x41 0xc1 select without atn sequence 0x42 0xc2 select with atn sequence 0x43 0xc3 select with atn and stop sequence 0x44 0xc4 enable selection and reselection 0x45 disable selection and reselection 0x46 0xc6 select with atn3 sequence 0x47 0xc7 reselect3 sequence
disconnected state command group 5-7 copyright 1995?002 by lsi logic corporation. all rights reserved. 5.3.2 select without atn sequence this command causes the fsc initiator to arbitrate for the bus, enter the selection phase when it wins, and send the command descriptor block (cdb). the 6-, 10-, or 12-byte cdb must have either been placed in the fifo previously by the microprocessor, or must be transferred by dma, which involves setting the transfer count to 6, 10, or 12 and programming the external dma controller. in either case, the time-out and destination bus id registers must have been programmed previously. this command terminates early if a reselection time-out occurs, the target does not assert command phase or the target removes command phase too early. if it terminates normally, a function complete and bus service interrupt is generated. 5.3.3 select with atn sequence this command causes the fsc initiator to arbitrate for the bus, select a device with atn/ true, then send one message phase byte followed by 6, 10, or 12 command phase bytes. the message and command bytes must have either been placed in the fifo by the microprocessor or must be transferred by dma, which involves setting the transfer count to 7, 11, or 13 and programming the external dma controller. in either case, the time-out and destination bus id registers must have previously been programmed. this command terminates early if a select time-out occurs, the target does not assert message out phase followed by command phase, or the target removes command phase early. if it completes normally, a function complete and bus service interrupt are generated. 5.3.4 select with atn and stop sequence this command should be used in place of select with atn when multiple message phase bytes are to be sent (for example, a synchronous negotiation message). the command selects a target with atn/ asserted, sends one message phase byte that had previously been stored in the fifo, generates a bus service interrupt and a function complete interrupt, and stops. after the interrupt, the fifo may be ?led with other message bytes. a transfer information command then transfers bytes with atn/ true until the fifo empties. if a dma transfer information command is used, atn/ remains true until the transfer counter decrements to zero.
5-8 command set copyright 1995?002 by lsi logic corporation. all rights reserved. table 5.4 lists the target selected without atn sequence. table 5.5 lists the target selected with atn sequence, scsi-2 bit not set. table 5.4 target selected without atn sequence sequence step [2:0] interrupt register [7:0] interpretation 0 0 0 0 0 0 0 0 0 0 1 selected, loaded bus id into fifo, loaded null-byte message into fifo. 0 0 1 0 0 0 0 0 0 0 1 stopped in command phase due to parity error; some command descriptor block bytes may not have been received; check fifo ?gs. 0 0 1 0 0 0 1 0 0 0 1 same as previous; initiator asserted atn/ during command phase. 0 1 0 0 0 0 0 0 0 0 1 selected, received entire command descriptor block; check valid group code bit. 0 1 0 0 0 0 1 0 0 0 1 same as previous; initiator asserted atn/ during command phase. table 5.5 target selected with atn sequence (scsi-2 bit not set) sequence step [2:0] interrupt register [7:0] interpretation 0 0 0 0 0 0 0 0 0 1 0 selected with atn/, stored bus id and one message byte; stopped due to either parity error or invalid id message. 0 0 0 0 0 0 1 0 0 1 0 selected with atn/, stored bus id and one message byte; stopped because atn/ remained true after first message byte. 0 0 1 0 0 0 0 0 0 1 0 stopped in command phase due to parity error; some cdb bytes not received; check valid group code bit and fifo flags. 0 0 1 0 0 0 1 0 0 1 0 stopped in command phase; parity error and atn/ true. 0 1 0 0 0 0 0 0 0 1 0 selection complete; received one message byte and the entire command descriptor block. 0 1 0 0 0 0 1 0 0 1 0 same as previous; initiator asserted atn/ during command phase.
disconnected state command group 5-9 copyright 1995?002 by lsi logic corporation. all rights reserved. table 5.6 lists the target selected with atn sequence, scsi-2 bit or queue tag enable bit set. table 5.6 target selected with atn sequence (scsi-2 bit or queue tag enable bit set) sequence step [2:0] interrupt register [7:0] interpretation 0 0 0 0 0 0 0 0 0 1 0 selected with atn/, stored bus id and one message byte; stopped due to either parity error or invalid id message. 0 0 1 0 0 0 0 0 0 1 0 initiator released atn/ after one message byte received. stopped in command phase due to parity error; some cdb bytes not received; check valid group code bit and fifo flags. 0 0 1 0 0 0 1 0 0 1 0 initiator released atn/ after one message byte received. stopped in command phase; parity error and atn/ true. 0 1 0 0 0 0 0 0 0 1 0 initiator released atn/ after one message byte received. selection complete; received one message byte and the entire command descriptor block. 0 1 0 0 0 0 1 0 0 1 0 same as previous, initiator asserted atn/ during command phase. 1 0 0 0 0 0 0 0 0 1 0 parity error during second or third message byte. 1 0 0 0 0 0 1 0 0 1 0 atn/ remained true after third message byte, or atn/ remained true and invalid queue tagged message (if queue tagged enable bit is set). 1 0 1 0 0 0 0 0 0 1 0 received three message bytes, then stopped in command phase due to parity error; some cdb bytes not received; check valid group code bit and fifo ?gs. 1 0 1 0 0 0 1 0 0 1 0 stopped in command phase; parity error and atn/ true. 1 1 0 0 0 0 0 0 0 1 0 selection complete; received three message bytes and the entire command descriptor block.
5-10 command set copyright 1995?002 by lsi logic corporation. all rights reserved. table 5.7 lists the initiator select without atn sequence. table 5.8 lists the initiator select with atn sequence. table 5.7 initiator select without atn sequence sequence step [2:0] interrupt register [7:0] interpretation 0 0 0 0 0 1 0 0 0 0 0 arbitration complete; selection time-out; disconnected. 0 1 0 0 0 0 1 1 0 0 0 arbitration and selection complete; stopped because target did not assert command phase. 0 1 1 0 0 0 1 1 0 0 0 stopped during command transfer because target prematurely changed phase. 1 0 0 0 0 0 1 1 0 0 0 select sequence complete. table 5.8 initiator select with atn sequence sequence step [2:0] interrupt register [7:0] interpretation 0 0 0 0 0 1 0 0 0 0 0 arbitration complete; selection time-out; disconnected. 0 0 0 0 0 0 1 1 0 0 0 arbitration and selection complete; stopped because target did not assert message out phase; atn/ still asserted by fsc. 0 1 0 0 0 0 1 1 0 0 0 arbitration, selection, and message out complete; sent one message byte with atn/ true, then released atn/; stopped because target did not assert command phase after message byte was sent. 0 1 1 0 0 0 1 1 0 0 0 stopped during command transfer due to premature phase change. some cdb bytes may not have been sent; check flfo ?gs. 1 0 0 0 0 0 1 1 0 0 0 selection with atn sequence complete. one message byte and all command bytes have been sent.
disconnected state command group 5-11 copyright 1995?002 by lsi logic corporation. all rights reserved. table 5.9 lists the initiator select with atn and stop sequence. 5.3.5 enable selection/reselection after receiving this command, the fsc responds to bus-initiated selection or reselection. a command that causes the fsc to select or reselect cancels this command. this command must be reissued within 250 ms after the fsc disconnects to preserve ansi-recommended timings. if dma is enabled, incoming information is placed in memory. if dma is not enabled, incoming information remains in the fifo. 5.3.6 select with atn3 sequence this command is similar to the select with atn command, but sends three message bytes instead of one. it causes the fsc initiator to arbitrate for the bus, select a device with atn/ true, send three message phase bytes, deassert atn/, then send 6, 10, or 12 command phase bytes. the message and command bytes must have either been placed in the fifo by the microprocessor or must be transferred by dma. this involves setting the transfer count to 9, 13, or 15 and programming the external dma controller. in either case, the time-out and destination bus id registers must have previously been programmed. this command terminates early if a selection time-out occurs; the target does not assert the message out phase followed by the command phase, or the target removes command phase early. if it completes normally, a function complete and bus service interrupt are generated. table 5.9 initiator select with atn and stop sequence sequence step [2:0] interrupt register [7:0] interpretation 0 0 0 0 0 1 0 0 0 0 0 arbitration complete; selection time-out; disconnected. 0 0 0 0 0 0 1 1 0 0 0 arbitration and selection complete; stopped because target did not assert message out phase; atn/ still asserted by fsc. 0 0 1 0 0 0 1 1 0 0 0 message out complete; sent one message byte; atn/ on.
5-12 command set copyright 1995?002 by lsi logic corporation. all rights reserved. 5.3.7 reselect3 sequence this command reselects an initiator and sends three message bytes: a one-byte identify message and a two-byte queue tag message. if dma is not enabled, the three message bytes must be loaded into the fifo before this command is issued. table 5.10 lists the initiator select with atn3 sequence. 5.4 initiator command group if the fsc is not in initiator state when it receives one of these commands, the command is ignored, an illegal command interrupt is generated, and the command register is cleared. refer to the description of the command register on page 4-8 . if bsy/ goes false while the fsc is connected as an initiator, it generates a disconnected interrupt. the interrupt output occurs 1.5 to 3.5 clk cycles after bsy/ goes false. table 5.10 initiator select with atn3 sequence sequence step [2:0] interrupt register [7:0] interpretation 0 0 0 0 0 1 0 0 0 0 0 arbitration complete; selection time-out; disconnected. 0 0 0 0 0 0 1 1 0 0 0 arbitration and selection complete; stopped because target did not assert message out phase; atn/ still asserted by fsc. 0 1 0 0 0 0 1 1 0 0 0 sent 1, 2, or 3 message bytes; stopped because target prematurely changed from message out phase or did not assert command phase after third message byte; atn/ released only if third message byte was sent. 0 1 1 0 0 0 1 1 0 0 0 stopped during command transfer due to premature phase change; some cdb bytes may not have been sent; check fifo ?gs. 1 0 0 0 0 0 1 1 0 0 0 selection with atn3 sequence complete. three message bytes and all command bytes were sent.
initiator command group 5-13 copyright 1995?002 by lsi logic corporation. all rights reserved. when the fsc receives the last byte of a message in phase, it leaves ack/ (acknowledge) asserted on the bus to prevent the target from sending any more bytes until the initiator decides to accept or reject the message. if the initiator accepts the command, it issues a message accepted command. if the initiator does not accept the message, a set atn command should be issued before the message accepted command, causing the target to change to message out phase. for non-dma commands, an empty fifo means that the last byte has been sent. for dma commands, the transfer counter signals the last byte. if parity checking is enabled and the fsc detects a parity error on an incoming scsi byte while in initiator mode, it automatically asserts atn/ prior to deasserting ack/ for the byte that has the error. the one exception is after a phase change to synchronous data in, and is described as follows. if the synchronous offset register is non-zero (synchronous) and the phase changes to data in, the dma interface is immediately disabled and the reporting of a parity error during data in phase is delayed. the phase change to data in latches the fifo flags to indicate how many bytes were in the fifo (these bytes are lost); clears the fifo; loads the fifo with the first data in byte; generates an interrupt; and continues to load the fifo with incoming data in bytes as long as the target sends them, but not more than the specified offset. to continue receiving data in bytes, the microprocessor would normally issue the transfer information command to re-enable the dma interface. if parity checking is enabled and a parity error occurred on a previous input phase (message in or status), then the parity error flag is set in the status register and atn/ is set on the scsi bus. if a parity error occurred during the data in phase, the parity bit is not set nor is atn/ asserted until after the fsc receives the subsequent transfer information command.
5-14 command set copyright 1995?002 by lsi logic corporation. all rights reserved. table 5.11 lists the initiator commands. 5.4.1 transfer information this command can send or receive any information phase bytes, but is most often used for data transfer. note: for synchronous transfer, dma must be used. the fsc continues to transfer information until one of the following terminating events occurs: ? transfer is complete. successful completion generates a bus service interrupt. for dma transfer information, the transfer is complete when the transfer counter decrements to zero, the fifo is empty and the target asserts req/ for the next byte. for non-dma transfer information in which the fsc is sending bytes to the scsi bus, the transfer is complete when the fifo empties and the target asserts req/ for the next byte. for non-dma transfer information in which the fsc is receiving bytes from the scsi bus, transfer is complete after one byte is received and the target asserts req/ for the next byte. thus non-dma transfer information commands generate an interrupt for every byte received. table 5.11 initiator commands non-dma dma mnemonic 0x10 0x90 transfer information 0x11 0x91 initiator command complete sequence 0x12 message accepted 0x18 0x98 transfer pad 0x1a set atn 0x1b reset atn 0x1e set atn immediate
initiator command group 5-15 copyright 1995?002 by lsi logic corporation. all rights reserved. ? if the phase is message out, the fsc removes atn/ prior to asserting ack/ for the last byte of the message. for non-dma, the fifo ?gs indicate the last byte. for dma, the transfer counter indicates the last byte. ? target changes phase. the fsc clears the command register and generates a bus service interrupt after the target asserts req/ for the next byte. ? target releases bsy/ (busy). the fsc generates a disconnected interrupt. ? the fsc receives the last byte of a message in phase. (for non-dma, every byte is assumed to be the last byte. for dma, the transfer counter signals the last byte.) the fsc leaves ack/ asserted and generates a function complete interrupt. all message in and status phase transfers are handled one byte at a time. if dma is enabled, the next byte is not received until the current byte has been written to buffer memory and the fifo is empty. if dma is not enabled, each byte creates an interrupt. 5.4.2 initiator command complete sequence this command causes the fsc to receive a status byte followed by a message byte. it terminates early if the target does not assert the message in phase, or if the target disconnects. after receiving the message byte, the fsc leaves ack/ asserted on the bus to allow the initiator to assert atn/ if the message is unacceptable. 5.4.3 message accepted this command deasserts the ack/ signal on the scsi bus. any of the commands that receive bytes during message phase leave ack/ asserted after receiving the last message byte. to accept the message, issue this command. to reject the message, set atn/ and then issue this command.
5-16 command set copyright 1995?002 by lsi logic corporation. all rights reserved. 5.4.4 transfer pad transfer pad is usually an error recovery technique. it is useful when a target requests more bytes than an initiator has to send, or when an initiator must receive and discard a number of bytes from a target. when transmitting to the scsi bus, transfer pad ?ls the fifo with null bytes and sends them to the scsi bus. when receiving from the scsi bus, transfer pad receives bytes, places them on the top of the fifo, and discards them from the bottom of the fifo. when sending pad bytes to the scsi bus, dma must be enabled. no dma requests are actually made, but the fsc uses the transfer counter to end the transfer. the command terminates under the same conditions as the section 5.4.1, ?ransfer information, command, except that the fsc does not leave ack/ asserted on the last byte of a message in phase. if the command terminates before the transfer counter reaches zero (due to phase change or disconnect) the fifo may contain pad bytes. 5.4.5 set atn this command asserts attention on the scsi bus. no interrupt is generated from this command. atn/ stays asserted until the last byte of a message out phase. this command does not pre-empt a command in progress; attention is asserted after the current command is completed. dma commands use the transfer counter to indicate the last byte. for non-dma commands, the last byte means that the fifo is empty. for dma transfers, the last byte means that the transfer counter is zero. atn/ is also released if the target disconnects prematurely. 5.4.6 reset atn this command causes atn/ to be released. it does not cause an interrupt. this command must not be used when connected to a device supporting the common command set (ccs). the fsc obeys ccs protocol by releasing atn/ on the last byte of a message out phase. the reset atn command is provided for older devices that do not respond properly to the atn/ condition.
target command group 5-17 copyright 1995?002 by lsi logic corporation. all rights reserved. 5.4.7 set atn immediate this command asserts attention on the scsi bus while another command is in progress. this command does not terminate a currently executing command, but allows the fsc as initiator to alert the target to go to message out phase at the earliest convenience. atn/ deasserts at the last message out byte or when a reset atn command is issued. 5.5 target command group if the fsc receives any of these commands when it is not in target state, it ignores the command, clears the command register, and generates an illegal command interrupt. refer to the command register description on page 4-8 for details. normal completion of these commands causes a function complete interrupt. if atn is asserted, the bus service bit is set in the status register and an interrupt is generated. if the fsc was idle when atn was asserted, a bus service interrupt is generated, the function complete bit is zero, and the command register is cleared.
5-18 command set copyright 1995?002 by lsi logic corporation. all rights reserved. table 5.12 lists the target commands. 5.5.1 send message this command causes the fsc to assert message in phase and sends bytes until the fifo is empty or the transfer counter is zero (if dma). 5.5.2 send status this command causes the fsc to assert status phase and sends bytes until the fifo is empty or the transfer counter is zero (if dma). 5.5.3 send data this command causes the fsc to assert data in phase and sends bytes until the fifo is empty, or the transfer counter is zero and the fifo is empty (if dma). dma must be used for synchronous transfers. table 5.12 target commands non-dma dma mnemonic 0x20 0xa0 send message 0x21 0xa1 send status 0x22 0xa2 send data 0x23 0xa3 disconnect sequence 0x24 0xa4 terminate sequence 0x25 0xa5 target command complete sequence 0x27 disconnect 0x28 0xa8 receive message 0x29 0xa9 receive command 0x2a 0xaa receive data 0x2b 0xab receive command sequence 0x04 target abort dma
target command group 5-19 copyright 1995?002 by lsi logic corporation. all rights reserved. 5.5.4 disconnect sequence this command causes the fsc to assert message in phase, send two bytes, then disconnect from the scsi bus. normally, the ?st byte is a save data pointers message, and the second byte is a disconnect message. these bytes must be loaded into the fifo by the microprocessor, or may be loaded by dma. if atn/ is asserted by the initiator, the bus service and function complete bits are set and an interrupt is generated, but the fsc does not disconnect. table 5.13 lists the target disconnect sequence. 5.5.5 terminate sequence this command causes the fsc ?st to assert status phase, send one byte; then assert message in phase, send one more byte, and disconnect. these bytes must be loaded into the fifo by the microprocessor, or may be loaded by dma. if atn/ is asserted by the initiator, the bus service and function complete bits are set and an interrupt is generated, but the fsc does not disconnect. if atn/ is not asserted by the initiator, a disconnect interrupt is generated. table 5.13 target disconnect sequence sequence step [2:0] interrupt register [7:0] interpretation 0 0 0 0 0 0 1 1 0 0 0 sent one message byte; stopped because initiator set atn/. 0 0 1 0 0 0 1 1 0 0 0 sent two message bytes; stopped because initiator set atn/. 0 1 0 0 0 1 0 1 0 0 0 disconnect sequence complete; disconnected, bus is free.
5-20 command set copyright 1995?002 by lsi logic corporation. all rights reserved. table 5.14 lists the target terminate sequence. 5.5.6 target command complete sequence this command is similar to terminate sequence, but is used for linked commands. it causes the fsc ?st to assert status phase, send one byte, then assert message in phase and send one more byte. the message byte is normally a command complete message. if atn/ is asserted by the initiator, the bus service and function complete bits are set and an interrupt is generated. if atn/ is not asserted by the initiator, a function complete interrupt is generated. in either case, the fsc does not disconnect. table 5.15 lists the target command complete sequence. 5.5.7 disconnect this command causes the fsc to release all scsi bus signals except rst/ (when triggered, rst/ is driven true for approximately 25 s, depending on clk frequency and the clock conversion factor). the fsc returns to the disconnected state without generating an interrupt. table 5.14 target terminate sequence sequence step [2:0] interrupt register [7:0] interpretation 0 0 0 0 0 0 1 1 0 0 0 sent one status byte; stopped because initiator set atn/. 0 0 1 0 0 0 1 1 0 0 0 sent status and message bytes; stopped because initiator set atn/. 0 1 0 0 0 1 0 1 0 0 0 terminate sequence complete; disconnected, bus is free. table 5.15 target command complete sequence sequence step [2:0] interrupt register [7:0] interpretation 0 0 0 0 0 0 1 1 0 0 0 sent one status byte; stopped because initiator set atn/. 0 0 1 0 0 0 1 1 0 0 0 sent status and message bytes; stopped because initiator set atn/. 0 1 0 0 0 0 0 1 0 0 0 command complete sequence complete.
target command group 5-21 copyright 1995?002 by lsi logic corporation. all rights reserved. 5.5.8 receive message this command causes the fsc to assert message out phase and receive bytes from the initiator. for a non-dma command, only one byte per interrupt may be received. a dma command interrupts after the transfer counter decrements to zero. this command terminates by generating a function complete interrupt. 5.5.9 receive command this command causes the fsc to assert command phase and receive bytes from the initiator. for non-dma receive command, only one byte per interrupt may be received. dma receive command interrupts after the transfer counter decrements to zero. this command terminates by generating a function complete interrupt. 5.5.10 receive data this command causes the fsc to assert data out phase and receive bytes from the initiator. for non-dma receive data, only one byte per interrupt may be received. dma receive data interrupts after the transfer counter decrements to zero and the fifo is empty. this command terminates by generating a function complete interrupt. dma must be used for synchronous transfers. 5.5.11 receive command sequence this command causes the fsc to assert command phase and receive a number of bytes, which vary according to the group code field of the first byte. if the scsi-2 bit is set in the con?uration 2 (con? 2) register, group 2 commands are recognized as 10-byte commands. if the scsi-2 bit is cleared, group 2 commands are recognized as reserved commands. groups 3 and 4 are always reserved. the fsc requests six bytes for reserved commands, six bytes for group 6 vendor unique commands, 10 bytes for group 7 vendor unique commands, and 12 bytes for group 5 commands.
5-22 command set copyright 1995?002 by lsi logic corporation. all rights reserved. table 5.16 lists the target receive command sequence. 5.5.12 target abort dma the target abort dma command allows the microprocessor to stop a target data transfer command whose progress has been halted due to inactivity on the dma channel. one potential application is a system containing a microprocessor and an intelligent buffer controller that handles buffer management. the microprocessor sets up the buffer controller and overprograms the transfer counter prior to issuing a scsi transfer command to the chip. when the buffer controller runs out of buffers, it interrupts the microprocessor. the microprocessor stops the chip and commands it to disconnect from the scsi bus. note: the target abort dma command should be used with extreme caution. before using this command, verify that the removal of dreq by this command does not confuse the systems dma controller. the abort dma command executes from the top of the command fifo. if there is a stacked command waiting to execute, it is overwritten and the gross error bit 6 ( status register) is set. the abort dma command clears itself from the command stack after being decoded. the abort dma command can only be used when all of the following conditions are true: ? either the target send data or target receive data command is operating ? the dma controller has halted table 5.16 target receive command sequence sequence step [2:0] interrupt register [7:0] interpretation 0 0 1 0 0 0 0 1 0 0 0 stopped during command transfer due to parity error; check fifo ?gs. 0 0 1 0 0 0 1 1 0 0 0 stopped during command transfer due to parity error; atn/ asserted by initiator. 0 1 0 0 0 0 0 1 0 0 0 received entire command descriptor block. 0 1 0 0 0 0 1 1 0 0 0 received entire cdb; initiator asserted atn/.
target command group 5-23 copyright 1995?002 by lsi logic corporation. all rights reserved. ? the chip is in a steady state: send data the dma fifo is empty receive asynchronous data the fifo is full (fifo flags register = 0x10), or the transfer counter is zero ( status register bit4=1) receive synchronous data the transfer counter is zero, or the offset counter is at maximum value ( sequence step register bit3=0) when these conditions are true, the chip halts with dreq asserted. if the chip is in synchronous transfer mode when halted, some ack/ responses from the scsi bus may not have been received and remain outstanding. upon receiving the abort dma command, the chip resets the dma interface, including the dreq output pin, and terminates the command in progress. the chip completes any ongoing scsi process. send asynchronous data transfers complete immediately. send synchronous data transfers complete when the offset counter is zero. receive asynchronous data transfers complete immediately. data left in the fifo should be removed by the microprocessor. receive synchronous data operations complete when all outstanding scsi ack/s have been received. no extra bits are set in the interrupt or status registers. the microprocessor receives the interrupt from the command that was in progress, and the command fifo is cleared.
5-24 command set copyright 1995?002 by lsi logic corporation. all rights reserved.
lsi53CF92A fast scsi controller 6-1 copyright 1995?002 by lsi logic corporation. all rights reserved. chapter 6 electrical speci?ations this chapter is divided into the following sections: ? section 6.1, ?c electrical characteristics ? section 6.2, ?olerant active negation technology speci?ations ? section 6.3, ?c electrical characteristics ? section 6.4, ?csi timing diagrams ? section 6.5, ?ackage drawings 6.1 dc electrical characteristics tables 6.1 through 6.5 describe the lsi53CF92A dc electrical characteristics. stresses beyond those listed in table 6.1 may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions section of this speci?ation is not implied. table 6.1 absolute maximum stress ratings symbol parameter pins min max unit test conditions t stg storage temperature ? 55 150 c v dd supply voltage ? 0.5 7.0 v v in input voltage v ss ? 0.5 v dd +0.5 v i lu latch-up current 100 ma ? 2v 6-2 electrical speci?ations copyright 1995?002 by lsi logic corporation. all rights reserved. table 6.2 recommended operating conditions symbol parameter pins min max unit test conditions v dd supply voltage 4.75 5.25 v i dd supply current 1 ma static 1 1. static means all inputs are deasserted, all outputs ?ating, and all bidirectional pins con?ured as inputs. i dd supply current 50 ma dynamic t a ambient temperature 0 70 c ja thermal resistance, junction/ambient 54 c/w t r rise time 2 2. the timing data applies to all pins without schmitt triggers. 1 v/ns t f fall time 2 1 v/ns table 6.3 inputs symbol parameter pins min max unit test conditions v ih input high voltage 2.0 v dd +0.5 v v il input low voltage v ss ?.5 0.8 v i in input leakage current non-scsi ? 10 10 a0 dc electrical characteristics 6-3 copyright 1995?002 by lsi logic corporation. all rights reserved. table 6.4 outputs symbol parameter pins min max unit test conditions v oh output high voltage dreq 2.4 v dd vi oh = ? 2ma v ol output low voltage dreq, int/ v ss 0.4 v i ol =4ma v ol output low voltage 1 1. tolerant active negation not enabled. rst/, sel/, ack/, req/, bsy/, sdp, sd[7:0] v ss 0.5 v i ol =48ma i oz high-z state leakage ? 10 10 a0 6-4 electrical speci?ations copyright 1995?002 by lsi logic corporation. all rights reserved. 6.2 tolerant active negation technology speci?ations table 6.6 provides electrical characteristics for se scsi signals. figures 6.1 through 6.5 provide reference information for testing scsi signals. table 6.6 tolerant active negation technology electrical characteristics 1 symbol parameter min type max unit test conditions v oh 2 output high voltage 2.5 3.1 3.5 v i oh = 2.5 ma v ol output low voltage 0.1 0.2 0.5 v i ol =48ma v ih input high voltage 2.0 7.0 v v il input low voltage ? 0.5 0.8 v referenced to v ss v ik input clamp voltage ? 0.66 ? 0.74 ? 0.77 v v dd = min; i i = ? 20 ma v th threshold, high to low 1.1 1.2 1.3 v v tl threshold, low to high 1.5 1.6 1.7 v v th ? tl hysteresis 300 350 400 mv i oh 2 output high current 2.5 15 24 ma v oh = 2.5 v i ol output low current 100 150 200 ma v ol = 0.5 v i osh 2 short-circuit output high current 625 ma output driving low, pin shorted to v dd supply 3 i osl short-circuit output low current 95 ma output driving high, pin shorted to v ss supply i lh input high leakage 0.05 10 a ? 0.5 < v dd < 5.25 v pin = 2.7 v i ll input low leakage ? 0.05 ? 10 a ? 0.5 < v dd < 5.25 v pin = 0.5v r i input resistance 20 m ? scsi pins 4 c p capacitance per pin 6 8 10 pf quad flat pack package t r 2 rise time, 10% to 90% 9.7 15.0 18.5 ns figure 6.1 t f fall time, 90% to 10% 5.2 8.1 14.7 ns figure 6.1 dv h /dt slew rate, low to high 0.15 0.23 0.49 v/ns figure 6.1 dv l /dt slew rate, high to low 0.19 0.37 0.67 v/ns figure 6.1 i lu latch-up 100 ma t 1 filter delay 20 25 30 ns figure 6.2 t 1 extended filter delay 40 50 60 ns figure 6.2 1. these values are guaranteed by periodic characterization. 2. active negation outputs only: data, parity, req/, ack/. 3. single pin only; irreversible damage may occur if sustained for one second. 4. scsi reset pin as 10 k ? pull-up resistor.
tolerant active negation technology speci?ations 6-5 copyright 1995?002 by lsi logic corporation. all rights reserved. figure 6.1 rise and fall time test conditions figure 6.2 scsi input filtering figure 6.3 hysteresis of scsi receivers + ? 2.5 v 47 ? 20 pf req/ or ack/ input t 1 v th note: t 1 is the input ?tering period, register programmable (bit 4 of the con?uration 3 (con? 3) register 0x0c to either 30 or 60 ns. 1 0 received logic level input voltage (volts) 1.1 1.3 1.5 1.7
6-6 electrical speci?ations copyright 1995?002 by lsi logic corporation. all rights reserved. figure 6.4 input current as a function of input voltage figure 6.5 output current as a function of output voltage 40 20 0 ? 20 ? 40 ? 4 0 4 8 12 16 ? 0.7 v 8.2 v high-z output active input voltage (volts) input current (milliamperes) 14.4 v output sink current (milliamperes) ? 800 ? 600 ? 400 ? 200 0 012345 output voltage (volts) output source current (milliamperes) 20 40 60 80 100 012345 output voltage (volts) 0
ac electrical characteristics 6-7 copyright 1995?002 by lsi logic corporation. all rights reserved. 6.3 ac electrical characteristics the ac characteristics described in this section apply over the operating voltage and temperature range, 4.75 v v dd 5.25 v and 0?c t a 70 ?c. output timing is based on simulation under worst-case conditions (4.75 v, 70 ?c) and worst-case processing using the following termination. all timing data in this speci?ation is taken from the 10% and 90% points with respect to the speci?d v ol and v oh of the waveforms. note: performance numbers are based upon the fsc operating with a 40 mhz clock. other clock inputs also allow for increased transfer rates in proportion to their frequencies. table 6.7 lists the pin terminations. table 6.7 pin terminations pin termination dreq, pad[7:0] 50 pf int/ 50 pf, 2.2 k ? pull-up db[7:0], dbp 80 pf sdp, sd[7:0], rst/, sel/, bsy/, atn/, msg/, cd/, io/, req/, ack/ 200 pf, 110 ? pull-up, 165 ? pull-down
6-8 electrical speci?ations copyright 1995?002 by lsi logic corporation. all rights reserved. figure 6.6 illustrates the clock input. table 6.8 lists the clock timing with the fastclk bit cleared, and table 6.9 lists the clock timing with the fastclk bit set. figure 6.6 clock input t cl t ch t cp t cs clk table 6.8 clock timing (fastclk bit cleared) symbol parameter min max unit notes t cpa clock frequency, asynchronous scsi 10 25 mhz 1 t cps clock frequency, synchronous scsi 12 25 mhz 1 t ch clock high time 0.4 t cp 0.6 t cp ns t cl clock low time 0.4 t cp 0.6 t cp ns t cp clock period 40 100 ns t cs synchronization latency = t cp +t cl t cp t cl +t cp 1. minimum frequencies to meet ansi timing speci?ations. table 6.9 clock timing (fastclk bit set) symbol parameter min max unit notes t cpa clock frequency, asynchronous scsi 25 40 mhz 1 t cps clock frequency, synchronous scsi 25 40 mhz 1 t ch clock high time 0.4 * t cp 0.6 * t cp ns t cl clock low time 0.4 * t cp 0.6 * t cp ns t cp clock period 25 40 ns t cs synchronization latency = t cp +t cl t cp t cl +t cp 1. minimum frequencies to meet ansi timing speci?ations.
ac electrical characteristics 6-9 copyright 1995?002 by lsi logic corporation. all rights reserved. figure 6.7 and table 6.10 provide reset timing data. figure 6.7 reset input t rst reset table 6.10 reset timing symbol parameter min max unit notes t rst reset pulse width 3 t cp ?s 1 1. at power-up, the reset pin must be asserted as v dd ?st becomes stable.
6-10 electrical speci?ations copyright 1995?002 by lsi logic corporation. all rights reserved. figure 6.8 and table 6.11 provide interrupt timing data. figure 6.8 interrupt output int/ rd/ t rih t ir t rd t ril table 6.11 interrupt timing symbol parameter min max unit notes t ir int/ low to interrupt register read 0 ns 1 t rd rd/ pulse width 30 ns 2 t rih rd/ low to int/ high 0 3 t cp +30 ns t ril rd/ high to int/ low t cs ?s 1. the interrupt register should not be read when int/ is false. 2. refer to the register read speci?ations for the timing requirements of cs/, rd/, and address for reading the interrupt register.
ac electrical characteristics 6-11 copyright 1995?002 by lsi logic corporation. all rights reserved. 6.3.1 register interface, nonmultiplexed pad bus figure 6.9 illustrates the register read, nonmultiplexed pad bus. figure 6.9 register read, nonmultiplexed pad bus figure 6.10 illustrates the register write, nonmultiplexed pad bus. figure 6.10 register write, nonmultiplexed pad bus a[3:0] cs/ rd/ pad[7:0] t 1 t 2 t 7 t 3 t 6 t 5 t 8 t 4 t 9 a[3:0] cs/ wr/ pad[7:0] t 1 t 2 t 12 t 3 t 11 t 10 t 13 t 15 t 14
6-12 electrical speci?ations copyright 1995?002 by lsi logic corporation. all rights reserved. table 6.12 lists the register interface, nonmultiplexed pad bus. table 6.12 register interface, nonmultiplexed pad bus symbol parameter min max unit notes t 1 address setup to cs/ low 3 ns 1 t 2 address hold from cs/ low 20 ns t 3 cs/ high to cs/ low t cp +5 ns 2 t 4 cs/ low to read data valid t cp +30 ns 3 t 5 cs/ setup to rd/ low 0 ns 4, 5 t 6 rd/ pulse width 30 ns t 7 rd/ high to cs/ high 0 ns 4 t 8 rd/ low to data valid 30 ns 6 t 9 rd/ high to data bus disable 2 30 ns t 10 cs/ setup to wr/ low 0 ns 5, 7 t 11 wr/ pulse width 30 ns t 12 wr/ high to cs/ high 0 ns 7 t 13 data setup to wr/ high 15 ns t 14 data hold after wr/ high 4 ns t 15 cs/ or wr/ high to cs/ or wr/ high 3t cp ?s 1. cs/ must make a high to low transition to latch a new register address. 2. t 3 minimum is (2 * 3 t cp + 5) for successive fifo reads or a fifo write/read followed by a read of the fifo flags register. 3. t 8 must also be satis?d. 4. if rd/ is held low, the time from cs/ low to stable data is t 4 and the output disable time from cs/ high is t 9 . 5. if dma is active, the fifo must not be accessed. 6. t 4 must also be satis?d. 7. if wr/ is held low, the data setup to cs/ high is t 13 minimum; data hold from cs/ high is t 13 minimum.
ac electrical characteristics 6-13 copyright 1995?002 by lsi logic corporation. all rights reserved. 6.3.2 register interface, multiplexed pad bus figure 6.11 illustrates the register read, multiplexed pad bus. figure 6.11 register read, multiplexed pad bus figure 6.12 illustrates the register write, multiplexed pad bus. figure 6.12 register write, multiplexed pad bus ale cs/ rd/ t 3 t 4 pad[7:0] t 6 t 9 t 7 t 8 address t 2 t 1 data t 10 t 5 t 11 ale cs/ wr/ t 3 t 4 pad[7:0] t 6 t 12 t 13 address t 2 t 1 data t 18 t 15 address data t 14 t 16 t 17
6-14 electrical speci?ations copyright 1995?002 by lsi logic corporation. all rights reserved. table 6.13 lists the register interface, multiplexed pad bus. table 6.13 register interface, multiplexed pad bus symbol parameter min max unit notes t 1 address setup to ale low 10 ns t 2 address hold from ale low 10 ns t 3 ale pulse width 20 ns 1 t 4 ale low to cs/ low 10 ns t 5 cs/ low to data valid t cp +30 ns 2 t 6 cs/ high to ale high 0 ns t 7 cs/ setup to rd/ low 0 ns 3, 4 t 8 rd/ pulse width 30 ns t 9 rd/ high to cs/ high 0 ns 4 t 10 rd/ low to data valid 30 ns 5 t 11 rd/ high to data bus disable 2 30 ns t 12 cs/ setup to wr/ low 0 ns 3, 6 t 13 wr/ pulse width 30 ns t 14 wr/ high to cs/ high 0 ns 6 t 15 data setup to wr/ high 15 ns t 16 data hold from wr/ high 4 ns t 17 wr/ high to ale high t cp +5 ns 7 t 18 cs/ or wr/ high to cs/ or wr/ high 3t cp ?s 1. ale must pulse to capture a new register address. 2. t 10 must also be satis?d. 3. if dma is active, the fifo register must not be accessed. 4. if rd/ is held low, the time from cs/ low to stable data is t 5 and the data release time from cs/ high is t 11 . 5. t 5 must also be satis?d. 6. if wr/ is held low, data setup to cs/ high is t 15 and data hold from cs/ high is t 16 minimum. 7. t 17 minimum is (2 *3 t cp + 5) for successive fifo reads or a fifo write/read followed by a read of the fifo flags register.
ac electrical characteristics 6-15 copyright 1995?002 by lsi logic corporation. all rights reserved. 6.3.3 dma interface (nonmultiplexed mode only) figure 6.13 illustrates the dma read, nonmultiplexed mode only. figure 6.13 dma read, nonmultiplexed mode only figure 6.14 illustrates the dma write, nonmultiplexed mode only. figure 6.14 dma write, nonmultiplexed mode only dreq dack/ t 3 db[7:0], t 2 t 5 t 6 t 8 dbp t 1 t 7 t 4 dreq dack/ dbwr/ t 1 db[7:0], t 2 t 10 t 14 t 12 t 3 t 11 dbp t 6 t 4 t 5 t 9 t 13
6-16 electrical speci?ations copyright 1995?002 by lsi logic corporation. all rights reserved. table 6.14 lists the dma interface, nonmultiplexed mode only. table 6.14 dma interface (nonmultiplexed mode only) 1 symbol parameter min max unit notes t 1 dack/ low to dreq low 30 ns 2 t 2 dack/ high to dreq high 30 ns t 3 dack/ high to dack/ low t cp +5 ns 3, 4 t 4 dack/ pulse width t cp +5 ns t 5 dack/ period (low to low) 3 t cp ?s t 6 dack/ period (high to high) 3 t cp ?s t 7 dack/ low to data valid 30 ns t 8 dack/ high to data bus disable 2 30 ns t 9 dack/ low to dbwr/ low 0 ns 4 t 10 dbwr/ pulse width 30 ns t 11 dbwr/ high to dack/ high 0 ns 4 t 12 data setup to dbwr/ 15 ns t 13 data hold from dbwr/ 4 ns t 14 dbwr/ high to dbwr/ low 30 ns 1. alternate dma is disabled. 2. dreq may stay high if the fifo has room to accept another byte during dma write, or send another byte during dma read. if the current dma acknowledge cycle ?ls the fifo (write) or empties the fifo (read), then dreq goes low. 3. dack/ must toggle once for each access. 4. dbwr/ edges may precede or follow dack/ edges. recommended values are: t g 0 and t 11 0. if dbwr/ is held low, the data setup to dack/ high is 15 ns minimum; data hold from dack/ high is 4 ns minimum.
ac electrical characteristics 6-17 copyright 1995?002 by lsi logic corporation. all rights reserved. 6.3.4 dma interface (multiplexed mode only) figure 6.15 illustrates the dma read, multiplexed mode only. figure 6.15 dma read, multiplexed mode only figure 6.16 illustrates the dma write, multiplexed mode only. figure 6.16 dma write, multiplexed mode only dreq dack/ dbrd/ t 1 db[7:0], t 2 t 8 t 10 dbp t 4 t 5 t 7 t 3 t 11 t 9 t 6 dreq dack/ dbwr/ t 1 db[7:0], t 2 t 13 t 17 t 15 t 3 t 14 dbp t 6 t 4 t 5 t 12 t 16
6-18 electrical speci?ations copyright 1995?002 by lsi logic corporation. all rights reserved. table 6.15 lists the dma interface, multiplexed mode only. table 6.15 dma interface (multiplexed mode only) 1 symbol parameter min max unit notes t 1 dack/ low to dreq low 30 ns 2 t 2 dack/ high to dreq high 30 ns 2 t 3 dack/ high to dack/ low t cp +5 ns 3 t 4 dack/ pulse width t cp +5 ns t 5 dack/ period (low to low) 3 t cp ?s t 6 dack/ period (high to high) 3 t cp ?s t 7 dack/ low to dbrd/ low 0 ns 4 t 8 dbrd/ pulse width 30 ns t 9 dbrd/ high to dack/ high 0 ns 4 t 10 dbrd/ to data valid 0 30 ns t 11 dbrd/ high to data bus disable 2 30 ns t 12 dack/ low to dbwr/ low 0 ns 5 t 13 dbwr/ pulse width 30 ns t 14 dbwr/ high to dack/ high 0 ns 5 t 15 data setup to dbwr/ high 15 ns t 16 data hold from dbwr/ high 4 ns t 17 dbwr/ high to dbwr/ low 30 ns 1. alternate dma is disabled. 2. dreq may stay high if the fifo has room to accept another byte during dma write, or send another byte during dma read. if the current dma acknowledge cycle ?ls the fifo (write) or empties the fifo (read), then dreq goes low. 3. dack/ must toggle once for each access. 4. dbrd/ trailing edge may precede or follow dack/ trailing edge. the recommended value is: t 9 0. if dbrd/ is held low past dack/, the time from dack/ low to stable data is 30 ns maximum, and the time from dack/ high to data bus disable is 2 ns minimum and 25 ns maximum. 5. dbwr/ trailing edge may precede or follow dack/ trailing edge. the recommended value is: t 14 0. if dbwr/ is past dack/, the data setup to dack/ high is 10 ns minimum; data hold from dack/ high is 10 ns minimum.
ac electrical characteristics 6-19 copyright 1995?002 by lsi logic corporation. all rights reserved. 6.3.5 burst mode dma interface (multiplexed mode) figure 6.17 illustrates the burst mode dma read, multiplexed mode only. figure 6.17 burst mode dma read, multiplexed mode only figure 6.18 illustrates burst mode dma write, multiplexed mode only. figure 6.18 burst mode dma write, multiplexed mode only dreq dack/ dbrd/ t 2 db[7:0], t 12 dbp t 1 t 11 t 10 t 3 t 8 t 6 t 7 t 9 t 5 t 4 dreq dack/ dbwr/ t 2 db[7:0], t 21 dbp t 1 t 20 t 19 t 3 t 17 t 15 t 16 t 18 t 14 t 13
6-20 electrical speci?ations copyright 1995?002 by lsi logic corporation. all rights reserved. table 6.16 lists the burst mode dma interface, multiplexed mode. table 6.16 burst mode dma interface (multiplexed mode) symbol parameter min max unit notes t 1 dack/ high to dreq high 30 ns 1 t 2 dack/ low to dreq low 30 ns 2 t 3 dack/ high to dack/ low t cp +5 ns t 4 dbrd/ high to dreq low 2 t cp +t cl +30 ns 3 t 5 dack/ low to dbrd/ low 0 ns t 6 dbrd/ pulse width t cp +5 ns t 7 dbrd/ high to dbrd/ low t cp +5 ns t 8 dbrd/ low to data valid 30 ns t 9 dbrd/ high to data bus disable 30 ns t 10 dbrd/ low to dbrd/ low 3 t cp ?s t 11 dbrd/ high to dbrd/ high 3 t cp ?s t 12 dbrd/ high to dack/ high 0 ns t 13 dbwr/ high to dreq low 2 t cp +t cl +30 ns 3 t 14 dack/ low to dbwr/ low 0 ns t 15 dbwr/ pulse width t cp +5 ns t 16 dbwr/ high to dbwr/ low t cp +5 ns t 17 data setup to dbwr/ high 10 ns t 18 data hold from dbwr/ high 4 ns t 19 dbwr/ low to dbwr/ low 3 t cp ?s t 20 dbwr/ high to dbwr/ high 3 t cp ?s t 21 dbwr/ high to dack/ high 0 ns 1. assertion pending. if the fifo is empty during dma read, or full during dma write, then assertion is not pending. 2. single dma transfer only. 3. multiple dma transfers only.
ac electrical characteristics 6-21 copyright 1995?002 by lsi logic corporation. all rights reserved. 6.3.6 burst mode dma interface (nonmultiplexed mode) figure 6.19 illustrates the burst mode dma read, nonmultiplexed mode only. figure 6.19 burst mode dma read, nonmultiplexed mode only figure 6.20 illustrates the burst mode dma write, nonmultiplexed mode only. figure 6.20 burst mode dma write, nonmultiplexed mode only dreq dack/ t 2 db[7:0], dbp t 8 t 3 t 4 t 6 t 7 t 9 t 5 t 1 dreq dack/ dbwr/ t 10 db[7:0], dbp t 14 t 13 t 17 t 11 t 12 t 18 t 16 t 1 t 15
6-22 electrical speci?ations copyright 1995?002 by lsi logic corporation. all rights reserved. table 6.17 lists the burst mode dma interface, nonmultiplexed mode. table 6.17 burst mode dma interface (nonmultiplexed mode) symbol parameter min max unit notes t 1 dack/ high to dreq high 30 ns 1 t 2 dack/ low to dreq low 30 ns 2 t 3 dack/ pulse width t cp +5 ns 3 t 4 dack/ high to dack/ low t cp +5 ns t 5 dack/ low to data valid 30 ns t 6 dack/ high to data bus disable 30 ns t 7 dack/ low to dack/ low 3 t cp ?s 3 t 8 dack/ high to dack/ high 3 t cp ?s 3 t 9 dack/ high to dreq low 2 t cp +t cl +30 ns 4 t 10 dbwr/ low to dreq low 30 ns 2, 5 t 11 dbwr/ pulse width t cp +5 ns 5 t 12 dbwr/ high to dbwr/ low t cp +5 ns 5 t 13 dbwr/ low to dbwr/ low 3 t cp ?s 5 t 14 dbwr/ high to dbwr/ high 3 t cp ?s 5 t 15 dbwr/ high to dreq low 2 t cp +t cl +30 ns 4, 5 t 16 dack/ low to dbwr/ low 0 ns 5, 6 t 17 data setup to dbwr/ high 15 ns 5 t 18 data hold from dbwr/ high 4 ns 5 1. assertion pending. if the fifo is empty during dma read, or full during dma write, then assertion is not pending. 2. single dma transfer only. 3. dack/ is used for dma reads and writes. for dma reads, dack/ must toggle, and is assumed to be coincident with an external read signal. 4. multiple dma transfers only. 5. either dack/ or dbwr/ may toggle during a burst write. timings are shown for dbwr/ toggling; however, dack/ and dbwr/ may be interchanged in figure 6.20 and table 6.17 . 6. dbwr/ low may precede dack/ low.
scsi timing diagrams 6-23 copyright 1995?002 by lsi logic corporation. all rights reserved. 6.4 scsi timing diagrams figures 6.21 through 6.26 and tables 6.18 through 6.23 describe the lsi53CF92A scsi timing. figure 6.21 initiator asynchronous send sd[7:0], t 1 sd0 ack/ req/ t 4 t 2 t 3 table 6.18 initiator asynchronous send timings symbol parameter min max unit t 1 data setup to ack/ low 60 ns t 2 ack/ high from req/ high 10 ns t 3 data hold from req/ high 5 ns t 4 ack/ low from req/ low 10 ns
6-24 electrical speci?ations copyright 1995?002 by lsi logic corporation. all rights reserved. figure 6.22 initiator asynchronous receive req/ t 3 ack/ sd[7:0], t 1 sd0 t 2 t 4 table 6.19 initiator asynchronous receive timings symbol parameter min max unit t 1 data setup to req/ low 0 ns t 2 ack/ low from req/ low 10 ns t 3 data hold from ack/ low 0 ns t 4 ack/ high from req/ high 10 ns
scsi timing diagrams 6-25 copyright 1995?002 by lsi logic corporation. all rights reserved. figure 6.23 target asynchronous send sd[7:0], t 1 sd0 req/ ack/ t 2 t 3 t 4 table 6.20 target asynchronous send timings symbol parameter min max unit t 1 data setup to req/ low 60 ns t 2 req/ high from ack/ low 10 ns t 3 data hold from ack/ low 5 ns t 4 req/ low from ack/ high 10 ns
6-26 electrical speci?ations copyright 1995?002 by lsi logic corporation. all rights reserved. figure 6.24 target asynchronous receive req/ t 4 ack/ sd[7:0], t 3 -sd0 t 1 t 2 table 6.21 target asynchronous receive timings symbol parameter min max unit t 1 req/ high from ack/ low 10 ns t 2 req/ low from ack/ high 10 ns t 3 data setup to ack/ low 0 ns t 4 data hold from req/ high 0 ns
scsi timing diagrams 6-27 copyright 1995?002 by lsi logic corporation. all rights reserved. figure 6.25 target and initiator synchronous output figure 6.26 target and initiator synchronous input sdx req/, t 2 ack/ t 3 t 4 t 1 sdx req/, t 6 ack/ t 7 t 8 t 5
6-28 electrical speci?ations copyright 1995?002 by lsi logic corporation. all rights reserved. table 6.22 scsi-1 se transfers (5 mbytes/s) symbol parameter min max unit t 1 req/ or ack/ assertion period 90 ns t 2 req/ or ack/ negation period 90 ns t 3 data setup to req/ or ack/ low 65 ns t 4 data hold from ack/ or req/ low 100 ns t 5 req/ or ack/ assertion period 90 ns t 6 req/ or ack/ negation period 90 ns t 7 data setup to req/ low or ack/ low 0 ns t 8 data hold from req/ low or ack/ low 45 ns table 6.23 fast scsi-2 se transfers (10 mbytes/s) symbol parameter min max unit t 1 req/ or ack/ assertion period 32 ns t 2 req/ or ack/ negation period 32 ns t 3 data setup to req/ or ack/ low 25 ns t 4 data hold from req/ or ack/ low 35 ns t 5 req/ or ack/ assertion period 20 ns t 6 req/ or ack/ negation period 20 ns t 7 data setup to req/ low or ack/ low 0 ns t 8 data hold from req/ low or ack/ low 10 ns
package drawings 6-29 copyright 1995?002 by lsi logic corporation. all rights reserved. 6.5 package drawings figure 6.27 is the 64-pin plastic quad flat pack package drawing and figure 6.28 is the 64-pin thin quad flat pack drawing for the lsi53CF92A. figure 6.27 64-pin plastic quad flat pack 17.2 0.25 14.0 0.10 17.2 0.25 14.0 0.10 pin 1 0 ? 0 min 0.40 min 0.25 max 2.10 max 2.35 max seating plane 1.60 ref. 0.80 0.15 0.13 min 0.30 min 0.45 max 0.80 bsc. pin 17 pin 33 pin 49 64-pin plastic quad flat pack
6-30 electrical speci?ations copyright 1995?002 by lsi logic corporation. all rights reserved. figure 6.28 64-pin thin quad flat pack 12.0 bsc. 10.0 bsc. 12.0 bsc. 10.0 bsc. pin 1 0 ? 0 min 0.20 min 0.10 0.05 1.40 0.05 1.60 max seating plane 1.00 ref. 0.60 0.15 0.09 min 0.17 min 0.27 max 0.50 bsc. pin 17 pin 33 pin 49 64-pin thin quad flat pack
lsi53CF92A fast scsi controller a-1 copyright 1995?002 by lsi logic corporation. all rights reserved. appendix a register map this is the register map for the registers in chapter 4, ?egisters. table a.1 register map register name address read/write page clock conversion 0x09 write only 4-26 command 0x03 read/write 4-8 con?uration 1 (con? 1) 0x08 read/write 4-24 con?uration 2 (con? 2) 0x0b read/write 4-28 con?uration 3 (con? 3) 0x0c read/write 4-30 con?uration 4 (con? 4) 0x0d read/write 4-34 destination bus id 0x04 write only 4-13 fifo 0x02 read/write 4-7 fifo flags 0x07 read only 4-21 interrupt 0x05 read only 4-14 reserved 0x0f 4-36 sequence step 0x06 read only 4-17 status 0x04 read only 4-10 synchronous offset 0x07 write only 4-21 synchronous transfer period 0x06 write only 4-18 test 0x0a write only 4-27 time-out 0x05 write only 4-16 transfer counter 0x00?x01 write only 4-4
a-2 register map copyright 1995?002 by lsi logic corporation. all rights reserved. transfer counter 0x00?x01 read only 4-5 transfer counter high/id 0x0e read/write 4-35 scam register set scsi bus control lines (sbcl) 0x0b read only 4-41 scsi bus data lines (sbdl) 0x0f read only 4-42 scsi control (scontrol) 0x08 read/write 4-37 scsi output control latch (socl) 0x0a read/write 4-40 scsi output data latch (sodl) 0x0e read/write 4-42 scsi status (sstatus) 0x09 read only 4-39 table a.1 register map (cont.) register name address read/write page
lsi53CF92A fast scsi controller b-1 copyright 1995?002 by lsi logic corporation. all rights reserved. appendix b wiring diagram figure b.1 single-pin, se scsi bus interface wiring diagram dbp db7 db6 db5 db4 db3 db2 db1 db0 cs/ rd/ wr/ dbwr/ dreq dack/ a3/ale a2/dbrd/ a1 a0 pad7 pad6 pad5 pad4 pad3 pad2 pad1 pad0 int/ reset clk mode lsi53CF92A + 5 v 2.2 k ? 10?0 mhz sdp sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 sdp/ sd7/ sd6/ sd5/ sd4/ sd3/ sd2/ sd1/ sd0/ sel/ bsy/ req/ ack/ msg/ cd/ io/ atn/ rst/ sel/ bsy/ req/ ack/ msg/ cd/ io/ atn/ rst/ dma controller/ microprocessor interface scsi bus
b-2 wiring diagram copyright 1995?002 by lsi logic corporation. all rights reserved.
lsi53CF92A fast scsi controller ix-1 copyright 1995?002 by lsi logic corporation. all rights reserved. index a asynchronous operation 2-14 b bus configuration modes multiplexed 2-8 nonmultiplexed 2-9 bus initiated sequences bus initiated reselection 2-5 bus initiated reset 2-6 bus initiated selection 2-4 stacked commands 2-6 c chip reset disconnect reset 2-17 hard reset 2-15 soft reset 2-16 clock conversion register 4-26 clock conversion bits 4-26 command register 4-8 command code bits 4-9 enable dma bit 4-9 command set disconnected state command group disable selection/reselection 5-11 enable selection/reselection 5-11 reselect sequence 5-6 reselect3 sequence 5-12 select with atn and stop sequence 5-7 select with atn sequence 5-7 select with atn3 sequence 5-11 select without atn sequence 5-6 illegal commands stacked commands 5-3 initiator command group initiator command complete sequence 5-15 message accepted 5-15 reset atn 5-16 set atn 5-16 set atn immediate 5-17 transfer information 5-14 transfer pad 5-16 miscellaneous command group flush fifo 5-4 nop 5-4 reset chip 5-4 reset scsi bus 5-5 target command group disconnect 5-20 disconnect sequence 5-19 receive command 5-21 receive command sequence 5-21 receive data 5-21 receive message 5-21 send data 5-18 send message 5-18 send status 5-18 target abort dma 5-22 target command complete sequence 5-20 terminate sequence 5-19 configuration 1 register 4-24 chip test mode enable bit 4-25 enable parity checking bit 4-25 my bus id bits 4-25 parity test mode bit 4-24 scsi reset reporting disable interrupt bit 4-24 slow cable mode bit 4-24 configuration 2 register 4-28 dma parity enable bit 4-30 dreq high impedance bit 4-28 features enable bit 4-28 scsi-2 bit 4-29 target bad parity abort bit 4-30 configuration 3 register 4-30 alternate dma mode bit 4-32 cdb10 bit 4-31 fast scsi bit 4-31 fastclk bit 4-32 id message reserved check bit 4-30 queue tag enable bit 4-31 threshold eight bit 4-33 configuration 4 register 4-34 enable active negation bit 4-35 d destination bus id register destination id bits 4-13 destination id register 4-13 disconnect reset 2-17 dma burst mode 2-11 deassertion of dreq 2-12 dma read 2-12 dma write 2-13 dma operation dma burst mode 2-11 dma threshold 2-9 normal dma mode 2-9
ix-2 index copyright 1995?002 by lsi logic corporation. all rights reserved. threshold eight mode 2-10 dma threshold 2-9 e electrical characteristics 6-6 tolerant specifications 6-6 electrical specifications ac electrical characteristics 6-7 burst mode dma interface (multiplexed mode) 6-19 burst mode dma interface (nonmultiplexed mode) 6-21 dma interface (multiplexed mode only) 6-17 dma interface (nonmultiplexed mode only) 6-15 pin terminations 6-7 register interface, multiplexed pad bus 6-13 register interface, nonmultiplexed pad bus 6-11 dc electrical characteristics absolute maximum stress ratings 6-1 bidirectional pins 6-3 inputs 6-2 recommended operating conditions 6-2 tolerant specifications electrical characteristics 6-4 f features 1-3 fifo flags register 4-21 fifo flags remaining bits 4-21 sequence step bits 4-21 fifo register 4-7 g general description 1-1 h hard reset 2-15 host bus configuration multiplexed bus configuration mode 2-8 nonmultiplexed bus configuration mode 2-9 i interrupt register 4-14 bus service bit 4-15 disconnect bit 4-14 function complete bit 4-15 illegal command bit 4-14 reselected bit 4-15 scsi reset detected bit 4-14 selected with atn bit 4-15 m multiplexed bus configuration mode 2-8 n nonmultiplexed bus configuration mode 2-9 normal dma mode 2-9 p parity checking and generation 2-6 parity control 2-7 r register bits clock conversion register clock conversion bits 4-26 command register command code bits 4-9 enable dma bit 4-9 configuration 1 register chip test mode enable bit 4-25 enable parity checking bit 4-25 my bus id bits 4-25 parity test mode bit 4-24 scsi reset reporting interrupt disable bit 4-24 slow cable mode bit 4-24 configuration 2 register dma parity enable bit 4-30 dreq high impedance bit 4-28 features enable bit 4-28 scsi-2 bit 4-29 target bad parity abort bit 4-30 configuration 3 register alternate dma mode bit 4-32 cdb10 bit 4-31 fast scsi bit 4-31 fastclk bit 4-32 id message reserved check bit 4-30 queue tag enable bit 4-31 threshold eight bit 4-33 configuration 4 register enable active negation bit 4-35 destination bus id register destination id bits 4-13 fifo flags register fifo bytes remaining bits 4-21 sequence step bits 4-21 interrupt register bus service bit 4-15 disconnect bit 4-14 function complete bit 4-15 illegal command bit 4-14 reselected bit 4-15 scsi reset detected bit 4-14 selected with atn bit 4-15 scsi bus control lines (sbcl) register scsi ack/ asserted bit 4-41 scsi atn/ asserted bit 4-41 scsi bsy/ asserted bit 4-41 scsi c/d/ asserted bit 4-41 scsi i/o/ asserted bit 4-41 scsi msg/ asserted bit 4-41 scsi req/ asserted bit 4-41 scsi sel/ asserted bit 4-41 scsi bus data lines (sbdl) register bits sd[7:0] 4-42 scsi control (scontrol) register arbitrate bit 4-38 assert data bus bit 4-38 enable delayed response to selection bit 4-37 enable scam selection response bit 4-38 low level bit 4-38
index ix-3 copyright 1995?002 by lsi logic corporation. all rights reserved. low level parity control bit 4-37 time-out test bit 4-37 scsi output control latch (socl) register assert scsi ack/ bit 4-40 assert scsi atn/ bit 4-40 assert scsi bsy/ bit 4-40 assert scsi c/d/ bit 4-40 assert scsi i/o/ bit 4-40 assert scsi msg/ bit 4-40 assert scsi req/ bit 4-40 assert scsi sel/ bit 4-40 scsi output data latch (sodl) register bits sd[7:0] 4-42 scsi status (sstatus) register arbitration delay1 bit 4-39 arbitration delay4 bit 4-39 scsi parity status bit 4-39 scsi reset status bit 4-39 sequence step register sequence step bits 4-17 synchronous offset max bit 4-17 status register parity error bit 4-11 terminal count bit 4-11 valid group code bit 4-12 test register all outputs to high impedance bit 4-27 initiator mode bit 4-27 target mode bit 4-27 transfer counter high/id register chip family id bits 4-36 chip revision level bits 4-36 register reset values, table 4-2 register set, table 4-3 registers scam registers scsi bus control lines (sbcl) 4-41 scsi bus data lines (sbdl) 4-42 scsi control (scontrol) 4-37 scsi output control latch (socl) 4-40 scsi output data latch (sodl) 4-42 scsi status (sstatus) 4-39 standard registers clock conversion 4-26 command 4-8 configuration 1 4-24 configuration 2 4-28 configuration 3 4-30 configuration 4 4-34 destination bus id 4-13 fifo 4-7 fifo flags 4-21 interrupt 4-14 sequence step 4-17 status 4-10 synchronous transfer period 4-18 test 4-27 time-out 4-16 transfer counter 4-4 , 4-5 transfer counter high/id 4-35 synchronous offset 4-21 reset levels disconnect reset 2-17 hard reset 2-15 soft reset 2-16 s scam 4-36 scam register set 4-36 scsi bus control lines (sbcl) register 4-41 scsi ack/ asserted bit 4-41 scsi atn/ asserted bit 4-41 scsi bsy/ asserted bit 4-41 scsi c/d/ asserted bit 4-41 scsi i/o/ asserted bit 4-41 scsi msg/ asserted bit 4-41 scsi req/ asserted bit 4-41 scsi sel/ asserted bit 4-41 scsi bus data lines (sbdl) register 4-42 bits sd[7:0] 4-42 scsi configured automatically (scam) capability 1-2 scsi control (scontrol) register 4-37 arbitrate bit 4-38 assert data bus bit 4-38 enable delayed response to selection bit 4-37 enable scam selection response bit 4-38 low level bit 4-38 low level parity control bit 4-37 time-out test bit 4-37 scsi data transfer rates asynchronous operation 2-14 synchronous operation 2-14 scsi operation 2-2 scsi output control latch (socl) register 4-40 assert scsi ack/ bit 4-40 assert scsi atn/ bit 4-40 assert scsi bsy/ bit 4-40 assert scsi c/d/ bit 4-40 assert scsi i/o/ bit 4-40 assert scsi msg/ bit 4-40 assert scsi req/ bit 4-40 assert scsi sel/ bit 4-40 scsi output data latch (sodl) register 4-42 bits sd[7:0] 4-42 scsi status (sstatus) register 4-39 arbitration delay1 bit 4-39 arbitration delay4 bit 4-39 scsi parity status bit 4-39 scsi reset status bit 4-39 scsi timings 6-23 sequence step register 4-17 sequence step bits 4-17 synchronous offset max bit 4-17 single-pin, single-ended scsi 2-13 soft reset 2-16 standard register set 4-4 status register 4-10 parity error bit 4-11 terminal count bit 4-11 valid group code bit 4-12 synchronous offset register 4-21 synchronous operation 2-14 synchronous transfer period register 4-18 t test register 4-27 all outputs to high impedance bit 4-27 initiator mode bit 4-27 target mode bit 4-27 threshold eight mode 2-10
ix-4 index copyright 1995?002 by lsi logic corporation. all rights reserved. time-out register 4-16 tolerant specifications 6-6 tolerant technology 1-2 transfer counter high/id register 4-35 chip family id bits 4-36 chip revision level bits 4-36 transfer counter register 4-4 , 4-5
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